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References: <20210816073813.11715-1-Mason.Zhang@mediatek.com>
In-Reply-To: <20210816073813.11715-1-Mason.Zhang@mediatek.com>
From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Tue, 24 Aug 2021 15:15:28 +0200
Message-ID: <CAPDyKFpSOcX6End_L0mLRt61s0aS_zT19snM71j9bxgMi1oUuA@mail.gmail.com>
Subject: Re: [PATCH 1/1] mmc: mediatek: fixed clk contrl flow
To:     Mason Zhang <Mason.Zhang@mediatek.com>
Cc:     Chaotian Jing <chaotian.jing@mediatek.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        linux-mmc <linux-mmc@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        wsd_upstream@mediatek.com
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Precedence: bulk

On Mon, 16 Aug 2021 at 09:39, Mason Zhang <Mason.Zhang@mediatek.com> wrote:
>
> this patch fixed clk contrl flow in set clk rate, no need close clk src,
> gate cg is enough, so no need call clk prepare/unprepare.

No, this isn't the way we should deploy clock support in drivers.

If the driver doesn't need to gate/ungate clocks from atomic context,
the proper thing is to use the slow path APIs, clk_prepare_enable()
and clk_disable_unprepare().

Kind regards
Uffe

>
> Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com>
> ---
>  drivers/mmc/host/mtk-sd.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 4dfc246c5f95..d9835b272c1f 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -895,9 +895,9 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>          * So if want to only gate src_clk, need gate its parent(mux).
>          */
>         if (host->src_clk_cg)
> -               clk_disable_unprepare(host->src_clk_cg);
> +               clk_disable(host->src_clk_cg);
>         else
> -               clk_disable_unprepare(clk_get_parent(host->src_clk));
> +               clk_disable(clk_get_parent(host->src_clk));
>         if (host->dev_comp->clk_div_bits == 8)
>                 sdr_set_field(host->base + MSDC_CFG,
>                               MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
> @@ -907,9 +907,9 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
>                               MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
>                               (mode << 12) | div);
>         if (host->src_clk_cg)
> -               clk_prepare_enable(host->src_clk_cg);
> +               clk_enable(host->src_clk_cg);
>         else
> -               clk_prepare_enable(clk_get_parent(host->src_clk));
> +               clk_enable(clk_get_parent(host->src_clk));
>
>         while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
>                 cpu_relax();
> --
> 2.18.0
>