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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id z131sm20601519pfc.159.2021.08.24.09.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Aug 2021 09:48:36 -0700 (PDT) Date: Tue, 24 Aug 2021 16:48:31 +0000 From: Sean Christopherson To: Xiaoyao Li Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/5] KVM: VMX: Disallow PT MSRs accessing if PT is not exposed to guest Message-ID: References: <20210824110743.531127-1-xiaoyao.li@intel.com> <20210824110743.531127-5-xiaoyao.li@intel.com> <8b53fc19-c3cc-d11f-37e3-70fc0639878d@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8b53fc19-c3cc-d11f-37e3-70fc0639878d@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 24, 2021, Xiaoyao Li wrote: > On 8/24/2021 10:20 PM, Sean Christopherson wrote: > > On Tue, Aug 24, 2021, Xiaoyao Li wrote: > > > Per SDM, it triggers #GP for all the accessing of PT MSRs, if > > > X86_FEATURE_INTEL_PT is not available. > > > > > > Signed-off-by: Xiaoyao Li > > > --- > > > arch/x86/kvm/vmx/vmx.c | 20 ++++++++++++++------ > > > 1 file changed, 14 insertions(+), 6 deletions(-) > > > > > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > > > index 4a70a6d2f442..1bbc4d84c623 100644 > > > --- a/arch/x86/kvm/vmx/vmx.c > > > +++ b/arch/x86/kvm/vmx/vmx.c > > > @@ -1010,9 +1010,16 @@ static unsigned long segment_base(u16 selector) > > > static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) > > > { > > > return vmx_pt_mode_is_host_guest() && > > > + guest_cpuid_has(&vmx->vcpu, X86_FEATURE_INTEL_PT) && > > > !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); > > > } > > > +static inline bool pt_can_read_msr(struct kvm_vcpu *vcpu) > > > +{ > > > + return vmx_pt_mode_is_host_guest() && > > > + guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT); > > > +} > > > + > > > static inline bool pt_output_base_valid(struct kvm_vcpu *vcpu, u64 base) > > > { > > > /* The base must be 128-byte aligned and a legal physical address. */ > > > @@ -1849,24 +1856,24 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > > &msr_info->data); > > > break; > > > case MSR_IA32_RTIT_CTL: > > > - if (!vmx_pt_mode_is_host_guest()) > > > + if (!pt_can_read_msr(vcpu)) > > > > These all need to provide exemptions for accesses from the host. KVM allows > > access to MSRs that are not exposed to the guest so long as all the other checks > > pass. > > Not all the MSRs are allowed to be accessed from host regardless of whether > it's exposed to guest. e.g., MSR_IA32_TSC_ADJUST, it checks guest CPUID > first. > > For me, for those PT MSRs, I cannot think of any reason that host/userspace > would access them without PT being exposed to guest. Order of operations. Userspace is allowed to do KVM_GET/SET_MSR before KVM_SET_CPUID2. > On the other hand, since this patch indeed breaks the existing userspace VMM > who accesses those MSRs without checking guest CPUID. > > So I will follow your advice to allow the host_initiated case in next > version. > > > Same for the next patch. > > Sorry, I don't know how it matters next patch. Me either. Ignore that comment. :-)