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Tue, 24 Aug 2021 10:16:40 -0700 Envelope-to: git@xilinx.com, peter.chen@kernel.org, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org Received: from [172.23.64.8] (port=48475 helo=xhdvnc108.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mIa2R-00004w-4f; Tue, 24 Aug 2021 10:16:39 -0700 Received: by xhdvnc108.xilinx.com (Postfix, from userid 16987) id 37CED604AC; Tue, 24 Aug 2021 22:46:30 +0530 (IST) From: Manish Narani To: , , CC: , , , Manish Narani , "Subbaraya Sundeep Bhatta" Subject: [PATCH 1/6] usb: chipidea: Add support for VBUS control with PHY Date: Tue, 24 Aug 2021 22:46:13 +0530 Message-ID: <1629825378-8089-2-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1629825378-8089-1-git-send-email-manish.narani@xilinx.com> References: <1629825378-8089-1-git-send-email-manish.narani@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 53f3cdc5-e229-442c-15cc-08d9672302b5 X-MS-TrafficTypeDiagnostic: SA1PR02MB8477: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3173; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2021 17:17:11.5254 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53f3cdc5-e229-442c-15cc-08d9672302b5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT039.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR02MB8477 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms make use of VBUS control over PHY which means controller driver has to access PHY registers to turn on/off VBUS line.This patch adds support for such platforms in chipidea. Signed-off-by: Subbaraya Sundeep Bhatta Signed-off-by: Michal Simek Signed-off-by: Manish Narani --- drivers/usb/chipidea/ci_hdrc_usb2.c | 1 + drivers/usb/chipidea/host.c | 9 +++++++++ drivers/usb/chipidea/otg_fsm.c | 7 +++++++ include/linux/usb/chipidea.h | 1 + 4 files changed, 18 insertions(+) diff --git a/drivers/usb/chipidea/ci_hdrc_usb2.c b/drivers/usb/chipidea/ci_hdrc_usb2.c index 89e1d82..dc86b12 100644 --- a/drivers/usb/chipidea/ci_hdrc_usb2.c +++ b/drivers/usb/chipidea/ci_hdrc_usb2.c @@ -30,6 +30,7 @@ static const struct ci_hdrc_platform_data ci_default_pdata = { static const struct ci_hdrc_platform_data ci_zynq_pdata = { .capoffset = DEF_CAPOFFSET, + .flags = CI_HDRC_PHY_VBUS_CONTROL, }; static const struct ci_hdrc_platform_data ci_zevio_pdata = { diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index e86d13c..578968d 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -63,6 +63,14 @@ static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable) priv->enabled = enable; } + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL && + ci->usb_phy && ci->usb_phy->set_vbus) { + if (enable) + ci->usb_phy->set_vbus(ci->usb_phy, 1); + else + ci->usb_phy->set_vbus(ci->usb_phy, 0); + } + if (enable && (ci->platdata->phy_mode == USBPHY_INTERFACE_MODE_HSIC)) { /* * Marvell 28nm HSIC PHY requires forcing the port to HS mode. @@ -71,6 +79,7 @@ static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable) hw_port_test_set(ci, 5); hw_port_test_set(ci, 0); } + return 0; }; diff --git a/drivers/usb/chipidea/otg_fsm.c b/drivers/usb/chipidea/otg_fsm.c index 6ed4b00..2f7f94d 100644 --- a/drivers/usb/chipidea/otg_fsm.c +++ b/drivers/usb/chipidea/otg_fsm.c @@ -471,6 +471,10 @@ static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on) return; } } + + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL) + ci->usb_phy->set_vbus(ci->usb_phy, 1); + /* Disable data pulse irq */ hw_write_otgsc(ci, OTGSC_DPIE, 0); @@ -480,6 +484,9 @@ static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on) if (ci->platdata->reg_vbus) regulator_disable(ci->platdata->reg_vbus); + if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL) + ci->usb_phy->set_vbus(ci->usb_phy, 0); + fsm->a_bus_drop = 1; fsm->a_bus_req = 0; } diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index edf3342..ee38835 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -62,6 +62,7 @@ struct ci_hdrc_platform_data { #define CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) #define CI_HDRC_IMX_IS_HSIC BIT(14) #define CI_HDRC_PMQOS BIT(15) +#define CI_HDRC_PHY_VBUS_CONTROL BIT(16) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 -- 2.1.1