Received: by 2002:a05:6a10:1d13:0:0:0:0 with SMTP id pp19csp2923341pxb; Tue, 24 Aug 2021 10:41:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwIRbhkJKOb4qSUa3bektB2v/7zvweRHKLUTzZUHYEE9S1wZEUkMtfsk/LTq7mITVqZsi5b X-Received: by 2002:a05:6638:4121:: with SMTP id ay33mr35099574jab.137.1629826898092; Tue, 24 Aug 2021 10:41:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629826898; cv=none; d=google.com; s=arc-20160816; b=xw+0Z7DW9w9HrxcVt0vijMhZnaSSwdRdH41NCxJHxAzOYMfGCTciWmMTHOKbuRAQgd N8jbwz/vcYgIkzeS1W7TPx5ZSS2M1vIHk7m81ifjSR/xhgX1w0ri4SoX73kyXuvOIC+J LQ0ZjtVgbs7IiBXt711LNaC47b7MFgdRsGZcOqJK9U95AqFQI5W3+ukAE/eHpwi/frTM oPYD/vLDuqEYyXxveGsFhq+MJIPzv3eJQxlGA6hwOk/fSUmQnFH7m0FmeVfhZZrz2P7F l1wjJGTOl6FIyySktF53PsIYGUA274mbiXNeZI9D2uhXiU5yzevoxPmHtnyIstmLPDYy +nPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SYtVJ2z3e4QqjyN8DY+pqT5oYutYyWA1jLwgAfIRdI8=; b=h7VbAsnxzlzD2yiP8WTbgYVd5qNuuXwRF68oBohAW3kNpnZ0k7QQno7guQ+XM0M0PQ Y+nooPuQxiC36/O4ENHnE+yP8dwISROhmrLIMiZDphVdp5RZDRD2QEkSzjvNP3K6VtAR 0fbbymp2z/7Hjt36kvXA8Y1/ttroadIf6a8lzDedx4dVLprje9OkfKqJz4svtoncVlrz RCE0SHTIyboeZMmdFa7EjQI8RNt+gxhFt/MAH3XhBKmox0iwNHShrqBO3lQkur/ode0l tCES94gs8MpFfvnNoAs5zijqQpAHIRTcNZkDYwiqS+pDalwyEPzgmWafIYzTQ5Z7EgR3 ik+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="jmyBia/S"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id b1si18543647ilj.117.2021.08.24.10.41.26; Tue, 24 Aug 2021 10:41:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="jmyBia/S"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238497AbhHXRkZ (ORCPT + 99 others); Tue, 24 Aug 2021 13:40:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:43450 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241764AbhHXRhP (ORCPT ); Tue, 24 Aug 2021 13:37:15 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8D57961BE6; Tue, 24 Aug 2021 17:07:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629824876; bh=dzRThOrU/QM7ctc3KKOny9Shr+VdAC6B4iog71J9TWQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jmyBia/S3D2dp8+eXepGx6oWw8TJUKJj0jJgq0erU5a+PiBP8ZxxJ5LVsjVHNR6No P5bkr3EzfEShoCTeN7YfkVMwaJc6oWXdkF2ULwduLYIQlWmhXlUC+DQGx4q6U65QWG hhysjHW80AB8SWtyu8J+uhYaszBJU9Q2FNuPuNQaJkoSWv+nklURXQYtgRUbwriljl ABlEl4zx8klKfkj0VuXuhrz2M9K6yKZWvyCVzTQ7/mtL47Dqvh0mPtNyVs38qIY15e iskTETJuipHhDcC5MO87j2PZ1a3xvU4OM/0iSbqKdgPMSkru/dLJZ1CN1gmn/jS4JN fZwkVGY+BkYEg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Thomas Gleixner , Kevin Tian , Marc Zyngier , Bjorn Helgaas , Greg Kroah-Hartman Subject: [PATCH 4.4 12/31] PCI/MSI: Enforce that MSI-X table entry is masked for update Date: Tue, 24 Aug 2021 13:07:24 -0400 Message-Id: <20210824170743.710957-13-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210824170743.710957-1-sashal@kernel.org> References: <20210824170743.710957-1-sashal@kernel.org> MIME-Version: 1.0 X-KernelTest-Patch: http://kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.4.282-rc1.gz X-KernelTest-Tree: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git X-KernelTest-Branch: linux-4.4.y X-KernelTest-Patches: git://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git X-KernelTest-Version: 4.4.282-rc1 X-KernelTest-Deadline: 2021-08-26T17:07+00:00 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thomas Gleixner commit da181dc974ad667579baece33c2c8d2d1e4558d5 upstream. The specification (PCIe r5.0, sec 6.1.4.5) states: For MSI-X, a function is permitted to cache Address and Data values from unmasked MSI-X Table entries. However, anytime software unmasks a currently masked MSI-X Table entry either by clearing its Mask bit or by clearing the Function Mask bit, the function must update any Address or Data values that it cached from that entry. If software changes the Address or Data value of an entry while the entry is unmasked, the result is undefined. The Linux kernel's MSI-X support never enforced that the entry is masked before the entry is modified hence the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Enforce the entry to be masked across the update. There is no point in enforcing this to be handled at all possible call sites as this is just pointless code duplication and the common update function is the obvious place to enforce this. Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Reported-by: Kevin Tian Signed-off-by: Thomas Gleixner Tested-by: Marc Zyngier Reviewed-by: Marc Zyngier Acked-by: Bjorn Helgaas Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210729222542.462096385@linutronix.de Signed-off-by: Greg Kroah-Hartman --- drivers/pci/msi.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 9cc4a598c652..208d7b179914 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -320,13 +320,26 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) if (dev->current_state != PCI_D0) { /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { - void __iomem *base; - base = entry->mask_base + - entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; + void __iomem *base = pci_msix_desc_addr(entry); + bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT); + + /* + * The specification mandates that the entry is masked + * when the message is modified: + * + * "If software changes the Address or Data value of an + * entry while the entry is unmasked, the result is + * undefined." + */ + if (unmasked) + __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT); writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); + + if (unmasked) + __pci_msix_desc_mask_irq(entry, 0); } else { int pos = dev->msi_cap; u16 msgctl; -- 2.30.2