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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id t42sm8940750pfg.30.2021.08.24.21.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Aug 2021 21:44:41 -0700 (PDT) Date: Tue, 24 Aug 2021 21:44:41 -0700 (PDT) X-Google-Original-Date: Tue, 24 Aug 2021 20:58:40 PDT (-0700) Subject: Re: [PATCH] riscv: Keep the riscv Kconfig selects sorted In-Reply-To: <20210805002908.2597836f@xhacker> CC: Paul Walmsley , aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: jszhang3@mail.ustc.edu.cn Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 04 Aug 2021 09:29:08 PDT (-0700), jszhang3@mail.ustc.edu.cn wrote: > From: Jisheng Zhang > > Move three Kconfig selects: ARCH_STACKWALK, ARCH_SUPPORTS_ATOMIC_RMW > and ARCH_SUPPORTS_DEBUG_PAGEALLOC to the right place. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/Kconfig | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 8fcceb8eda07..f133ac72572f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -13,9 +13,6 @@ config 32BIT > config RISCV > def_bool y > select ARCH_CLOCKSOURCE_INIT > - select ARCH_SUPPORTS_ATOMIC_RMW > - select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU > - select ARCH_STACKWALK > select ARCH_HAS_BINFMT_FLAT > select ARCH_HAS_DEBUG_VM_PGTABLE > select ARCH_HAS_DEBUG_VIRTUAL if MMU > @@ -33,6 +30,9 @@ config RISCV > select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > + select ARCH_STACKWALK > + select ARCH_SUPPORTS_ATOMIC_RMW > + select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU > select ARCH_SUPPORTS_HUGETLBFS if MMU > select ARCH_USE_MEMTEST > select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU Thanks, this is on for-next.