Received: by 2002:a05:6a10:1d13:0:0:0:0 with SMTP id pp19csp857202pxb; Wed, 25 Aug 2021 17:35:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz714SZIKCADgDxOsIPHFsC6H37X7ADTU+CvTnwXNdwOn2CxJxadb5uLIr//247LIPeUB5+ X-Received: by 2002:a17:906:d045:: with SMTP id bo5mr1381346ejb.461.1629938115853; Wed, 25 Aug 2021 17:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629938115; cv=none; d=google.com; s=arc-20160816; b=cxOVoUr8apT9WtqCrqs9ak/hNpJv5PXDpWA2MqKI9PxU+EP+YilBVdqor12ZZeuQ5z 41sXogPJ44y+AwEoUV0hyz5qtyOnLoQDXvDUxQQpLh+ln5jIECC1foLQNak24RlTp0/Y q7WEVakGCekXCnieY8iG9gEvKu6OlZZ5ErBKgwqPKoH3OW/ypVxEcLn0YTN3h0GjnLUY MCNKX2wKMBpvUUXtYNuv9RBhU79b7k0oO/8GZ1bgWsow/khTk21qTTBUva3j2BJSOA+E 1kENpGUrp5/fyxhexlGlPSB3On/+MlNkFQO22FwzDMQvhga0Fnb4WSIpJJIMW+50x0Xv WZhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version :dkim-signature; bh=ZDGvnYC2dH7Nt4/oe6iyRH1sh+gpvio2+swOAF5SWWM=; b=bbf9uSxtjGR3t1uhg4dRfu8q+BJADQKiXiTKvp9qKUlSItyJQZyvyhMxzqT4fAvoBN U0mEWnK6cbv7qS+2ZWEdZIXRPifWGf+a6rbDes2OR21VnV1bfJXr87ANjEi7d0182umn 4UJKTfV5DyJpo8Tv1MJvqkTyOQYe5MNIdAAyZe3y9rFTW7JVIyIJCb6lHzGluph4TvaX HM7zAqYGwGOWgL3Mmtdp+RhxMoWCzrdmu+mWvnvL7Uusd0qB11abKTEcQo6koMfxwz2W A0vukJ9GMFv34g5rcMaqW7wTlCS6AwjxggUXETVylJUulxjpQd3etHcvpc6KKzTuswSy FO6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QkYeFlxO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l15si992958ejg.444.2021.08.25.17.34.26; Wed, 25 Aug 2021 17:35:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QkYeFlxO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234396AbhHZAcI (ORCPT + 99 others); Wed, 25 Aug 2021 20:32:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:52406 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231210AbhHZAcH (ORCPT ); Wed, 25 Aug 2021 20:32:07 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E2297610D0; Thu, 26 Aug 2021 00:31:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629937880; bh=XFk+aK01AY+R2dj58lCttstlbncJMKuBtfKozV0XaIk=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=QkYeFlxOalO8NtPJPM5RhBh8j7Vk2Zi/9UTqamt6lR1JmceRcWO1Uxcmj9AJYi2WL BfXUFl6Lh4/+LO6SPiNnWNR0T08/oUuWRQccKiGhq40Bw0pX5zYDYYmZHRVgUZQju1 RYaIUmqxl1R6iWeI8/kYNwgVsw3GogsX9cX86tdiy7WCQI62kbTW6M10B9JTOTYmRE ZXLUVEbFSyEmiP2/JTA8qRcwzE7PlzW5Vuhf3imFCMVDFjcGuD9nNy/6erFSpI0OWv Z0YZmFtloHBVkgv7jaPurnVS4Tg6m5skjE085rnzXbw4M2kyZft8/o1Dwm55121Q2s 3WhmWQENq/tzA== Received: by mail-ed1-f50.google.com with SMTP id s25so1892283edw.0; Wed, 25 Aug 2021 17:31:20 -0700 (PDT) X-Gm-Message-State: AOAM533Ph60AVBBCBURm0Vmxh9+OFMrTKbb4RyEmFdUx5g9WMOhfujrH 6uIMwRFrWvse1A1ynlxZGkffMv51gZSILjZL9Q== X-Received: by 2002:aa7:ca04:: with SMTP id y4mr1341608eds.162.1629937879396; Wed, 25 Aug 2021 17:31:19 -0700 (PDT) MIME-Version: 1.0 References: <20210825102632.601614-1-enric.balletbo@collabora.com> <20210825122613.v3.3.Ifec72a83f224b62f24cfc967edfe78c5d276b2e3@changeid> In-Reply-To: <20210825122613.v3.3.Ifec72a83f224b62f24cfc967edfe78c5d276b2e3@changeid> From: Chun-Kuang Hu Date: Thu, 26 Aug 2021 08:31:08 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 3/7] dt-bindings: display: mediatek: add dsi reset optional property To: Enric Balletbo i Serra Cc: linux-kernel , Matthias Brugger , Hsin-Yi Wang , "moderated list:ARM/Mediatek SoC support" , Jitao Shi , Eizan Miyamoto , Nicolas Boichat , Chun-Kuang Hu , Collabora Kernel ML , Rob Herring , Daniel Vetter , David Airlie , Philipp Zabel , Rob Herring , DTML , DRI Development , Linux ARM Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Enric: Enric Balletbo i Serra =E6=96=BC 2021=E5=B9= =B48=E6=9C=8825=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=886:26=E5=AF=AB= =E9=81=93=EF=BC=9A > > Update device tree binding documentation for the dsi to add the optional > property to reset the dsi controller. Reviewed-by: Chun-Kuang Hu > > Signed-off-by: Enric Balletbo i Serra > Acked-by: Rob Herring > --- > > (no changes since v2) > > Changes in v2: > - Added a new patch to describe the dsi reset optional property. > > .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.t= xt > index 8238a86686be..3209b700ded6 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt > @@ -19,6 +19,11 @@ Required properties: > Documentation/devicetree/bindings/graph.txt. This port should be conne= cted > to the input port of an attached DSI panel or DSI-to-eDP encoder chip. > > +Optional properties: > +- resets: list of phandle + reset specifier pair, as described in [1]. > + > +[1] Documentation/devicetree/bindings/reset/reset.txt > + > MIPI TX Configuration Module > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D > > @@ -45,6 +50,7 @@ dsi0: dsi@1401b000 { > clocks =3D <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, > <&mipi_tx0>; > clock-names =3D "engine", "digital", "hs"; > + resets =3D <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; > phys =3D <&mipi_tx0>; > phy-names =3D "dphy"; > > -- > 2.30.2 >