Received: by 2002:a05:6a10:1d13:0:0:0:0 with SMTP id pp19csp397731pxb; Thu, 26 Aug 2021 05:54:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtU1B/gg66dNl5/aabDdkJ3LotTk+ksC0XyyT++jtsIgp2AwlCPOhJkS7xFR4Nml1L8wAl X-Received: by 2002:a6b:7710:: with SMTP id n16mr2930660iom.101.1629982484741; Thu, 26 Aug 2021 05:54:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629982484; cv=none; d=google.com; s=arc-20160816; b=rZ1jw024D29Eiy31/pa8X1t1W6RWDt/GIhXDCmssxYIDl89ZFr8B350nk35sGR/8+m sp3APPp+X8TwdSeR1jW1EpSrAd4UDgwe6Qhkn+1UPXnACM4rzrAonq3fveSIGBhs5wG4 aSLnTb/pCrn6XHYDBwPViP4q3epYpUiRKtRf0/1dpePTp2T5OSthIVNRCGIX3C1ls7Sc FPCzBaoM0Iu/YrhqoI5fi7mQAa9dOsbUPyXWy8OHWiaVLF9YSWnme+0fOCjUWR5bW1+b KrZM5olNi391W7q9leBJB8Sb1cT52O9EGAYCaLc9Jw9pkPotAtydvMUUU9xEBAOg6YUE J/vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=f6NbypYcKYkRQ6Q1yPnjaBtT4dOR8evtT2T5npnP4KM=; b=cNveWvm0vWhKF/sKwbM7L0Ll8PLizlAZkihGcVnA4GfiBks1EcrdkrNeBonfnpwib/ 66iJ8UQaW9alv3TFMwwaOg0hN8vI/gpH8zMC6KB7EhzqcTRNGVP2hNPoxM4MgM30lDg4 V+93fKcdcg8XQfxE4zQfMfOLUMbTxLOOyYynJdUXYBQmjgyI/VZ4H2wle8TJdzx5PlEm ki7UBOd3+07h6ClJCTcTSt5+J60WNAJfuQpmZ9tNwNQtXXz+/iZns9hzMjzsCjmbYyj0 tKfWpeM6CUQGQRdy0RD9JP41707n/H7o8Ex4yJcPfj6funhIs3SywuBiQL6fH59glIXI dHBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p17si2567117jak.93.2021.08.26.05.54.33; Thu, 26 Aug 2021 05:54:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242485AbhHZMyP (ORCPT + 99 others); Thu, 26 Aug 2021 08:54:15 -0400 Received: from foss.arm.com ([217.140.110.172]:46324 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237352AbhHZMyO (ORCPT ); Thu, 26 Aug 2021 08:54:14 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B998106F; Thu, 26 Aug 2021 05:53:27 -0700 (PDT) Received: from e123427-lin.arm.com (unknown [10.57.41.138]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA5143F766; Thu, 26 Aug 2021 05:53:23 -0700 (PDT) From: Lorenzo Pieralisi To: robh+dt@kernel.org, bhelgaas@google.com, Chuanjia Liu , matthias.bgg@gmail.com Cc: Lorenzo Pieralisi , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, yong.wu@mediatek.com, devicetree@vger.kernel.org, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org Subject: Re: [PATCH v12 0/6] PCI: mediatek: Spilt PCIe node to comply with hardware design Date: Thu, 26 Aug 2021 13:53:12 +0100 Message-Id: <162998235864.26306.15150607621994016843.b4-ty@arm.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210823032800.1660-1-chuanjia.liu@mediatek.com> References: <20210823032800.1660-1-chuanjia.liu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 23 Aug 2021 11:27:54 +0800, Chuanjia Liu wrote: > There are two independent PCIe controllers in MT2712 and MT7622 platform. > Each of them should contain an independent MSI domain. > > In old dts architecture, MSI domain will be inherited from the root > bridge, and all of the devices will share the same MSI domain.Hence that, > the PCIe devices will not work properly if the irq number which required > is more than 32. > > [...] Applied to pci/mediatek, thanks! [1/4] dt-bindings: PCI: mediatek: Update the Device tree bindings https://git.kernel.org/lpieralisi/pci/c/aa6eca5b81 [2/4] PCI: mediatek: Add new method to get shared pcie-cfg base address https://git.kernel.org/lpieralisi/pci/c/87e8657ba9 [3/4] PCI: mediatek: Add new method to get irq number https://git.kernel.org/lpieralisi/pci/c/436960bb00 [4/4] PCI: mediatek: Use PCI domain to handle ports detection https://git.kernel.org/lpieralisi/pci/c/77216702c8 Thanks, Lorenzo