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Date:   Thu, 26 Aug 2021 16:25:16 -0000
From:   tip-bot2 for =?utf-8?b?5ZGo55Cw5p2w?= (Zhou Yanjie) 
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Subject: [tip: timers/core] clocksource/drivers/ingenic: Use bitfield macro helpers
Cc:     zhouyanjie@wanyeetech.com, Paul Cercueil <paul@crapouillou.net>,
        Daniel Lezcano <daniel.lezcano@linaro.org>, x86@kernel.org,
        linux-kernel@vger.kernel.org
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The following commit has been merged into the timers/core branch of tip:

Commit-ID:     3b87265d825a2d29eb6b67511f0e7ed62225cd97
Gitweb:        https://git.kernel.org/tip/3b87265d825a2d29eb6b67511f0e7ed6222=
5cd97
Author:        =E5=91=A8=E7=90=B0=E6=9D=B0 (Zhou Yanjie) <zhouyanjie@wanyeete=
ch.com>
AuthorDate:    Fri, 30 Jul 2021 17:43:08 +08:00
Committer:     Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Sat, 14 Aug 2021 02:44:35 +02:00

clocksource/drivers/ingenic: Use bitfield macro helpers

Use "FIELD_GET()" and "FIELD_PREP()" to simplify the code.

[dlezcano] : Changed title

Signed-off-by: =E5=91=A8=E7=90=B0=E6=9D=B0 (Zhou Yanjie) <zhouyanjie@wanyeete=
ch.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/1627638188-116163-1-git-send-email-zhouyanjie=
@wanyeetech.com
---
 drivers/clocksource/ingenic-sysost.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clocksource/ingenic-sysost.c b/drivers/clocksource/ingen=
ic-sysost.c
index a129840..cb6fc2f 100644
--- a/drivers/clocksource/ingenic-sysost.c
+++ b/drivers/clocksource/ingenic-sysost.c
@@ -4,6 +4,7 @@
  * Copyright (c) 2020 =E5=91=A8=E7=90=B0=E6=9D=B0 (Zhou Yanjie) <zhouyanjie@=
wanyeetech.com>
  */
=20
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
@@ -34,8 +35,6 @@
 /* bits within the OSTCCR register */
 #define OSTCCR_PRESCALE1_MASK	0x3
 #define OSTCCR_PRESCALE2_MASK	0xc
-#define OSTCCR_PRESCALE1_LSB	0
-#define OSTCCR_PRESCALE2_LSB	2
=20
 /* bits within the OSTCR register */
 #define OSTCR_OST1CLR			BIT(0)
@@ -98,7 +97,7 @@ static unsigned long ingenic_ost_percpu_timer_recalc_rate(s=
truct clk_hw *hw,
=20
 	prescale =3D readl(ost_clk->ost->base + info->ostccr_reg);
=20
-	prescale =3D (prescale & OSTCCR_PRESCALE1_MASK) >> OSTCCR_PRESCALE1_LSB;
+	prescale =3D FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale);
=20
 	return parent_rate >> (prescale * 2);
 }
@@ -112,7 +111,7 @@ static unsigned long ingenic_ost_global_timer_recalc_rate=
(struct clk_hw *hw,
=20
 	prescale =3D readl(ost_clk->ost->base + info->ostccr_reg);
=20
-	prescale =3D (prescale & OSTCCR_PRESCALE2_MASK) >> OSTCCR_PRESCALE2_LSB;
+	prescale =3D FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale);
=20
 	return parent_rate >> (prescale * 2);
 }
@@ -151,7 +150,8 @@ static int ingenic_ost_percpu_timer_set_rate(struct clk_h=
w *hw, unsigned long re
 	int val;
=20
 	val =3D readl(ost_clk->ost->base + info->ostccr_reg);
-	val =3D (val & ~OSTCCR_PRESCALE1_MASK) | (prescale << OSTCCR_PRESCALE1_LSB);
+	val &=3D ~OSTCCR_PRESCALE1_MASK;
+	val |=3D FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale);
 	writel(val, ost_clk->ost->base + info->ostccr_reg);
=20
 	return 0;
@@ -166,7 +166,8 @@ static int ingenic_ost_global_timer_set_rate(struct clk_h=
w *hw, unsigned long re
 	int val;
=20
 	val =3D readl(ost_clk->ost->base + info->ostccr_reg);
-	val =3D (val & ~OSTCCR_PRESCALE2_MASK) | (prescale << OSTCCR_PRESCALE2_LSB);
+	val &=3D ~OSTCCR_PRESCALE2_MASK;
+	val |=3D FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale);
 	writel(val, ost_clk->ost->base + info->ostccr_reg);
=20
 	return 0;