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Date:   Sun, 29 Aug 2021 11:10:49 +0100
Message-ID: <87tuj8d0ie.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Huacai Chen <chenhuacai@gmail.com>
Cc:     Huacai Chen <chenhuacai@loongson.cn>,
        Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>,
        Xuefeng Li <lixuefeng@loongson.cn>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V3 08/10] irqchip: Add LoongArch CPU interrupt controller support
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On Sun, 29 Aug 2021 10:37:48 +0100,
Huacai Chen <chenhuacai@gmail.com> wrote:

> > Are you saying that there is no way for the interrupt controller
> > driver to figure out the hwirq number on its own?  That would seem
> > pretty odd (even the MIPS GIC has that). Worse case, you can provide
> > an arch-specific helper that exposes the current hwirq based on the
> > vector that triggered.
> We can get the hwirq number by reading CSR.ESTAT register, but in this
> way "vectored interrupts" is meaningless.

Let's face it, the way you use vectored interrupts makes zero sense
already. The whole point of vectored interrupts is that the CPU can
branch to the handler directly, making the interrupt handling cheaper
as there should be no additional decoding and you can run the final
handler immediately. Here, all your interrupts point to the same
"default handler"...

What do vectored interrupts bring? "Absolutely Nothing! (say it again!)"

	M.

-- 
Without deviation from the norm, progress is not possible.