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Mon, 30 Aug 2021 11:37:34 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mKfbY-007zfP-03; Mon, 30 Aug 2021 12:37:32 +0100 Date: Mon, 30 Aug 2021 12:37:31 +0100 Message-ID: <87pmtvcgec.wl-maz@kernel.org> From: Marc Zyngier To: Mark Kettenis Cc: devicetree@vger.kernel.org, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Nicolas Saenz Julienne , Jim Quinlan , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: Re: [PATCH v4 4/4] arm64: apple: Add PCIe node In-Reply-To: <20210827171534.62380-5-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> <20210827171534.62380-5-mark.kettenis@xs4all.nl> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.kettenis@xs4all.nl, devicetree@vger.kernel.org, alyssa@rosenzweig.io, kettenis@openbsd.org, tglx@linutronix.de, robh+dt@kernel.org, marcan@marcan.st, bhelgaas@google.com, nsaenz@kernel.org, jim2101024@gmail.com, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, daire.mcnamara@microchip.com, nsaenzjulienne@suse.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark, On Fri, 27 Aug 2021 18:15:29 +0100, Mark Kettenis wrote: > > From: Mark Kettenis > > Add node corresponding to the apcie,t8103 node in the > Apple device tree for the Mac mini (M1, 2020). > > Clock references and DART (IOMMU) references are left out at the > moment and will be added once the appropriate bindings have been > settled upon. > > Signed-off-by: Mark Kettenis > --- > arch/arm64/boot/dts/apple/t8103.dtsi | 63 ++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi > index 503a76fc30e6..6e4677bdef44 100644 > --- a/arch/arm64/boot/dts/apple/t8103.dtsi > +++ b/arch/arm64/boot/dts/apple/t8103.dtsi > @@ -214,5 +214,68 @@ pinctrl_smc: pinctrl@23e820000 { > , > ; > }; > + > + pcie0: pcie@690000000 { > + compatible = "apple,t8103-pcie", "apple,pcie"; > + device_type = "pci"; > + > + reg = <0x6 0x90000000 0x0 0x1000000>, > + <0x6 0x80000000 0x0 0x4000>, > + <0x6 0x81000000 0x0 0x8000>, > + <0x6 0x82000000 0x0 0x8000>, > + <0x6 0x83000000 0x0 0x8000>; > + reg-names = "config", "rc", "port0", "port1", "port2"; > + > + interrupt-parent = <&aic>; > + interrupts = , > + , > + ; > + > + msi-controller; > + msi-parent = <&pcie0>; > + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; > + > + bus-range = <0 3>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, > + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; > + > + pinctrl-0 = <&pcie_pins>; > + pinctrl-names = "default"; > + > + pci@0,0 { > + device_type = "pci"; > + reg = <0x0 0x0 0x0 0x0 0x0>; > + reset-gpios = <&pinctrl_ap 152 0>; > + max-link-speed = <2>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + }; > + > + pci@1,0 { > + device_type = "pci"; > + reg = <0x800 0x0 0x0 0x0 0x0>; > + reset-gpios = <&pinctrl_ap 153 0>; > + max-link-speed = <2>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + }; > + > + pci@2,0 { > + device_type = "pci"; > + reg = <0x1000 0x0 0x0 0x0 0x0>; > + reset-gpios = <&pinctrl_ap 33 0>; > + max-link-speed = <1>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + }; > + }; > }; > }; I have now implemented the MSI change on the Linux driver side, and it works nicely. So thumbs up from me on this front. I am now looking at the interrupts provided by each port: (1) a bunch of port-private interrupts (link up/down...) (2) INTx interrupts Given that the programming is per-port, I've implemented this as a per-port interrupt controller. (1) is dead easy to implement, and doesn't require any DT description. (2) is unfortunately exposing the limits of my DT knowledge, and I'm not clear how to model it. I came up with the following: port00: pci@0,0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 152 0>; max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; ranges; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&port00>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &port00 0>, <0 0 0 2 &port00 1>, <0 0 0 3 &port00 2>, <0 0 0 4 &port00 3>; }; which vaguely seem to do the right thing for the devices behind root ports, but doesn't seem to work for INTx generated by the root ports themselves. Any clue? Alternatively, I could move it to something global to the whole PCIe controller, but that doesn't seem completely right. It also begs the question whether the per-port interrupt to the AIC should be moved into each root port, should my per-port approach hold any water. Thanks, M. -- Without deviation from the norm, progress is not possible.