Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937517AbWLFTft (ORCPT ); Wed, 6 Dec 2006 14:35:49 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S937503AbWLFTfs (ORCPT ); Wed, 6 Dec 2006 14:35:48 -0500 Received: from smtp.osdl.org ([65.172.181.25]:60865 "EHLO smtp.osdl.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937339AbWLFTfr (ORCPT ); Wed, 6 Dec 2006 14:35:47 -0500 Date: Wed, 6 Dec 2006 11:34:52 -0800 (PST) From: Linus Torvalds To: Matthew Wilcox cc: Christoph Lameter , Russell King , David Howells , Andrew Morton , linux-arm-kernel@lists.arm.linux.org.uk, Linux Kernel Mailing List , linux-arch@vger.kernel.org Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch doesn't support it In-Reply-To: <20061206192647.GW3013@parisc-linux.org> Message-ID: References: <20061206164314.19870.33519.stgit@warthog.cambridge.redhat.com> <20061206192647.GW3013@parisc-linux.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1760 Lines: 43 On Wed, 6 Dec 2006, Matthew Wilcox wrote: > > Given parisc's paucity of atomic operations (load-and-zero-32bit and > load-and-zero-64bit), cmpxchg() is impossible to implement safely. > There has to be something we can hook to exclude another processor > modifying the variable. I'm OK with using atomic_cmpxchg(); we have > atomic_set locked against it. How do you to the atomic bitops? Also, I don't see quite why you think "cmpxchg()" and "atomic_cmpxchg()" would be different. ANY cmpxchg() needs to be atomic - if it's not, there's no point to the operation at all, since you'd just write it as if (*p == x) *p = y; instead, and not use cmpxchg(). So yes, architectures without native support (where "native" includes load-locked + store-conditional) always need to - on UP, just disable interrupts - on SMP, use a spinlock (with interrupts disabled), and share that spinlock with all the other atomic ops (bitops at a minimum - the "atomic_t" operations have traditionally been in another "locking space" because of sparc32 historic braindamage, but I'd suggest sharing the same spinlock between them all). And yeah, it sucks. You _can_ (if you really want to) make the spinlock be hashed based on the address of the atomic data structure. That at least allows you to do _multiple_ spinlocks, but let's face it, your real problem is _likely_ going to be cacheline bouncing, not contention, and then using a hashed lock won't be likely to buy you all that much. Linus - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/