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Date: Wed, 6 Dec 2006 11:47:40 -0800 (PST)
From: Christoph Lameter <clameter@sgi.com>
To: Matthew Wilcox <matthew@wil.cx>
cc: Linus Torvalds <torvalds@osdl.org>,
       Russell King <rmk+lkml@arm.linux.org.uk>,
       David Howells <dhowells@redhat.com>, Andrew Morton <akpm@osdl.org>,
       linux-arm-kernel@lists.arm.linux.org.uk,
       Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
       linux-arch@vger.kernel.org
Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch
 doesn't support it
In-Reply-To: <20061206193641.GY3013@parisc-linux.org>
Message-ID: <Pine.LNX.4.64.0612061147000.27534@schroedinger.engr.sgi.com>
References: <20061206164314.19870.33519.stgit@warthog.cambridge.redhat.com>
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 <Pine.LNX.4.64.0612061103260.3542@woody.osdl.org> <20061206192647.GW3013@parisc-linux.org>
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On Wed, 6 Dec 2006, Matthew Wilcox wrote:

> On Wed, Dec 06, 2006 at 11:29:42AM -0800, Christoph Lameter wrote:
> > On Wed, 6 Dec 2006, Matthew Wilcox wrote:
> > 
> > > It's just been pointed out to me that the parisc one isn't safe.
> > > 
> > > <dhowells> imagine variable X is set to 3
> > > <dhowells> CPU A issues cmpxchg(&X, 3, 5)
> > > <dhowells> you'd expect that to change X to 5
> > > <dhowells> but what if CPU B assigns 6 to X between cmpxchg reading X
> > > and it setting X?
> > 
> > The same could happen with a regular cmpxchg. Cmpxchg changes it to 5 and 
> > then other cpu performs a store before the next instruction.
> 
> For someone who's advocating use of cmpxchg, it seems you don't
> understand its semantics!  In the scenario dhowells pointed out, X would
> be left set to 5.  X should have the value 6 under any legitimate
> implementation:

Nope this is a UP implementation. There is no cpu B.

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