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From:   "Machnikowski, Maciej" <maciej.machnikowski@intel.com>
To:     Richard Cochran <richardcochran@gmail.com>
CC:     "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        "Brandeburg, Jesse" <jesse.brandeburg@intel.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "kuba@kernel.org" <kuba@kernel.org>,
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        "nikolay@nvidia.com" <nikolay@nvidia.com>,
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        "gustavoars@kernel.org" <gustavoars@kernel.org>,
        "Bross, Kevin" <kevin.bross@intel.com>,
        "Stanton, Kevin B" <kevin.b.stanton@intel.com>,
        Ahmad Byagowi <abyagowi@fb.com>
Subject: RE: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
Thread-Topic: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
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Date:   Tue, 31 Aug 2021 09:29:22 +0000
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> -----Original Message-----
> From: Richard Cochran <richardcochran@gmail.com>
> Sent: Monday, August 30, 2021 11:06 PM
> To: Machnikowski, Maciej <maciej.machnikowski@intel.com>
> Subject: Re: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL sta=
te
>=20
> On Fri, Aug 20, 2021 at 06:30:02PM +0000, Machnikowski, Maciej wrote:
>=20
> > So to be able to control SyncE we need 2 interfaces:
> > - Interface to enable the recovered clock output at the given pin
> > - interface to monitor the DPLL to see if the clock that we got is vali=
d, or
> not.
> >
> > If it comes to ESMC (G.8264) messages, SyncE itself can run in 2 modes
> (slides 29/30 will give you more details):
> > - QL-Disabled - with no ESMC messages - it base on the local informatio=
n
> from the PLL to make all decisions
> > - QL-Enabled - that adds ESMC and quality message transfer between the
> nodes.
>=20
> How do you get the QL codes from this?
>=20
> +enum if_eec_state {
> +       IF_EEC_STATE_INVALID =3D 0,
> +       IF_EEC_STATE_FREERUN,
> +       IF_EEC_STATE_LOCKACQ,
> +       IF_EEC_STATE_LOCKREC,
> +       IF_EEC_STATE_LOCKED,
> +       IF_EEC_STATE_HOLDOVER,
> +       IF_EEC_STATE_OPEN_LOOP,
> +       __IF_EEC_STATE_MAX,
> +};

This structure is for monitoring the lock state - or in other words - quali=
ty=20
of incoming sync signal.=20

The Locked state here means that the frequency used for transmitting the=20
data is syntonized with the input one. If something goes wrong, like the=20
frequency you recover from the link goes beyond the specified range or=20
the external signal is lost, the QL level will change accordingly.

The application layer running on top of this API needs to get the proper
QL level from the config file (just like the clockClass in PTP) and broadca=
st
it when the state is locked and switch to QL-DNU when you get out of=20
the lock state and expire preset hw-dependent holdover clock.

Also, if you are syntonizing to the SyncE clock you need to wait with
passing along QL-levels until the state reported by the EEC changes
to LOCKED.

Regards
Maciek