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Date:   Tue, 31 Aug 2021 20:59:18 +0530
From:   rajpat@codeaurora.org
To:     Stephen Boyd <swboyd@chromium.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, rnayak@codeaurora.org,
        saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com,
        skakit@codeaurora.org
Subject: Re: [PATCH V6 1/7] arm64: dts: sc7280: Add QSPI node
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On 2021-08-26 23:32, Stephen Boyd wrote:
> Can you please Cc folks who have reviewed prior series when you send
> again?
> 
> Quoting Rajesh Patil (2021-08-26 06:15:25)
>> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>> 
>> Add QSPI DT node and qspi_opp_table for SC7280 SoC.
> 
> Might be worth adding here that we put the opp table in / because SPI
> nodes assume any child node is a spi device and so we can't put the
> table underneath the spi controller.
> 

Okay

>> 
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 
>> ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 62 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..f8dd5ff 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1318,6 +1337,24 @@
>>                         };
>>                 };
>> 
>> +               qspi: spi@88dc000 {
>> +                       compatible = "qcom,qspi-v1";
>> +                       reg = <0 0x088dc000 0 0x1000>;
>> +                       #address-cells = <1>;
>> +                       #size-cells = <0>;
>> +                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> +                                <&gcc GCC_QSPI_CORE_CLK>;
>> +                       clock-names = "iface", "core";
>> +                       interconnects = <&gem_noc MASTER_APPSS_PROC 0
>> +                                       &cnoc2 SLAVE_QSPI_0 0>;
>> +                       interconnect-names = "qspi-config";
>> +                       power-domains = <&rpmhpd SC7280_CX>;
>> +                       operating-points-v2 = <&qspi_opp_table>;
>> +                       status = "disabled";
>> +
> 
> Nitpick: Drop newline above.

Okay

> 
>> +               };
>> +
>>                 dc_noc: interconnect@90e0000 {
>>                         reg = <0 0x090e0000 0 0x5080>;
>>                         compatible = "qcom,sc7280-dc-noc";