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[23.128.96.18]) by mx.google.com with ESMTP id b4si23757724ile.87.2021.09.01.01.21.23; Wed, 01 Sep 2021 01:21:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=Tu4E5xm1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243146AbhIAIUe (ORCPT + 99 others); Wed, 1 Sep 2021 04:20:34 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:24722 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243135AbhIAIUY (ORCPT ); Wed, 1 Sep 2021 04:20:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1630484368; x=1662020368; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=kOj1T/M9/T/1A0YLEYHMt7zmOnXmigoTevu8jxHooAU=; b=Tu4E5xm1etg3h9QUq3B8gBgmkYhT/92uukxMEX5i0tslaHJnhA3/eAL0 wY2Hpf3XFsf7U0Tai+eRt/PcV2C0NO65+seS94TLEO4SKB3sqKyxsQ4ia q9ywzeOedCTpzHMipvVy5lymFGZ3mKQFImFPOesLSMTKSmtrT/T5TPl1j I=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 01 Sep 2021 01:19:28 -0700 X-QCInternal: smtphost Received: from nalasex01c.na.qualcomm.com ([10.47.97.35]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 01:19:27 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.7; Wed, 1 Sep 2021 01:19:25 -0700 From: Fenglin Wu To: , , CC: , , , Yimin Peng Subject: [RESEND PATCH v1 7/9] spmi: pmic-arb: support updating interrupt type flags Date: Wed, 1 Sep 2021 16:18:08 +0800 Message-ID: <1630484290-28190-8-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1630484290-28190-1-git-send-email-quic_fenglinw@quicinc.com> References: <1630484290-28190-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yimin Peng Have the qpnpint_irq_set_type function clear unwanted high/low trigger bits when updating the interrupt flags. Signed-off-by: Yimin Peng Signed-off-by: Subbaraman Narayanamurthy Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 9239830..988204c 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -636,8 +636,12 @@ static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) type.type |= BIT(irq); if (flow_type & IRQF_TRIGGER_RISING) type.polarity_high |= BIT(irq); + else + type.polarity_high &= ~BIT(irq); if (flow_type & IRQF_TRIGGER_FALLING) type.polarity_low |= BIT(irq); + else + type.polarity_low &= ~BIT(irq); flow_handler = handle_edge_irq; } else { @@ -646,10 +650,13 @@ static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) return -EINVAL; type.type &= ~BIT(irq); /* level trig */ - if (flow_type & IRQF_TRIGGER_HIGH) + if (flow_type & IRQF_TRIGGER_HIGH) { type.polarity_high |= BIT(irq); - else + type.polarity_low &= ~BIT(irq); + } else { type.polarity_low |= BIT(irq); + type.polarity_high &= ~BIT(irq); + } flow_handler = handle_level_irq; } -- 2.7.4