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Subject: Re: [PATCH Part1 v5 34/38] x86/sev: Add snp_msg_seqno() helper
To:     Borislav Petkov <bp@alien8.de>
References: <20210820151933.22401-1-brijesh.singh@amd.com>
 <20210820151933.22401-35-brijesh.singh@amd.com> <YSkxxkVdupkyxAJi@zn.tnic>
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From:   Brijesh Singh <brijesh.singh@amd.com>
Message-ID: <01b9c0e8-a808-83a7-214f-ea62136ffa0b@amd.com>
Date:   Thu, 2 Sep 2021 10:27:38 -0500
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On 9/2/21 6:26 AM, Borislav Petkov wrote:
> On Mon, Aug 30, 2021 at 10:07:39AM -0500, Brijesh Singh wrote:
>> The SNP firmware spec says that counter must begin with the 1.
> 
> So put that in the comment and explain what 0 is: magic or invalid or
> whatnot and why is that so and that it is spec-ed this way, etc.
> 
> Just having it there without a reasoning makes one wonder whether that's
> some arbitrary limitation or so.

Agreed, I will add a comment explaining it.

> 
>> During the GHCB writing the seqno use to be 32-bit value and hence the GHCB
>> spec choose the 32-bit value but recently the SNP firmware changed it from
>> the 32 to 64. So, now we are left with the option of limiting the sequence
>> number to 32-bit. If we go beyond 32-bit then all we can do is fail the
>> call. If we pass the value of zero then FW will fail the call.
> 
> That sounds weird again. So make it 64-bit like the FW and fix the spec.
> 
>> I just choose the smaller name but I have no issues matching with the spec.
>> Also those keys does not have anything to do with the VMPL level. The
>> secrets page provides 4 different keys and they are referred as vmpck0..3
>> and each of them have a sequence numbers associated with it.
>>
>> In GHCB v3 we probably need to rework the structure name.
> 
> You can point to the spec section so that readers can find the struct
> layout there.
> 

I will add comment that this for spec 0.9+.

thanks