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From:   Daniel Baluta <daniel.baluta@oss.nxp.com>
To:     broonie@kernel.org, pierre-louis.bossart@linux.intel.com,
        lgirdwood@gmail.com, robh+dt@kernel.org,
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        peter.ujfalusi@linux.intel.com, alsa-devel@alsa-project.org,
        linux-kernel@vger.kernel.org, s-anna@ti.com,
        Daniel Baluta <daniel.baluta@nxp.com>
Subject: [PATCH v2 2/2] dt-bindings: dsp: fsl: Add DSP optional clocks documentation
Date:   Fri,  3 Sep 2021 17:53:40 +0300
Message-Id: <20210903145340.225511-3-daniel.baluta@oss.nxp.com>
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From: Daniel Baluta <daniel.baluta@nxp.com>

DSP node on the Linux kernel side must also take care of enabling
DAI/DMA related clocks.

By design we choose to manage DAI/DMA clocks from the kernel side because of
the architecture of some i.MX8 boards.

Clocks are handled by a special M4 core which runs a special firmware
called SCFW (System Controler firmware).

This communicates with A cores running Linux via a special Messaging
Unit and implements a custom API which is already implemented by the
Linux kernel i.MX clocks implementation.

Note that these clocks are optional. We can use the DSP without them.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
 .../devicetree/bindings/dsp/fsl,dsp.yaml      | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
index 7afc9f2be13a..1453668c0194 100644
--- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
+++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
@@ -24,16 +24,49 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 3
     items:
       - description: ipg clock
       - description: ocram clock
       - description: core clock
+      - description: esai0 core clock for accessing registers
+      - description: esai0 baud clock
+      - description: esai0 system clock
+      - description: esai0 spba clock required when ESAI is placed in slave mode
+      - description: SAI1 bus clock
+      - description: SAI1 master clock 0
+      - description: SAI1 master clock 1
+      - description: SAI1 master clock 2
+      - description: SAI1 master clock 3
+      - description: SAI3 bus clock
+      - description: SAI3 master clock 0
+      - description: SAI3 master clock 1
+      - description: SAI3 master clock 2
+      - description: SAI3 master clock 3
+      - description: SDMA3 root clock used for accessing registers
+
 
   clock-names:
+    minItems: 3
     items:
       - const: ipg
       - const: ocram
       - const: core
+      - const: esai0_core
+      - const: esai0_extal
+      - const: esai0_fsys
+      - const: esai0_spba
+      - const: sai1_bus
+      - const: sai1_mclk0
+      - const: sai1_mclk1
+      - const: sai1_mclk2
+      - const: sai1_mclk3
+      - const: sai3_bus
+      - const: sai3_mclk0
+      - const: sai3_mclk1
+      - const: sai3_mclk2
+      - const: sai3_mclk3
+      - const: smda3_root
 
   power-domains:
     description:
-- 
2.27.0