Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Fri, 3 Sep 2021 08:46:45 -0700
From:   Matthias Kaehlcke <mka@chromium.org>
To:     rajpat@codeaurora.org
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>, swboyd@chromium.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, rnayak@codeaurora.org,
        saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com,
        skakit@codeaurora.org
Subject: Re: [PATCH V5 1/7] arm64: dts: sc7280: Add QSPI node
Message-ID: <YTJDZRw1D444JCNt@google.com>
References: <1628754078-29779-1-git-send-email-rajpat@codeaurora.org>
 <1628754078-29779-2-git-send-email-rajpat@codeaurora.org>
 <YRUdccjvf+ivbqor@google.com>
 <d271d1dafe56cbb58d35a63ec6944b14@codeaurora.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
In-Reply-To: <d271d1dafe56cbb58d35a63ec6944b14@codeaurora.org>
Precedence: bulk

On Thu, Aug 26, 2021 at 06:29:41PM +0530, rajpat@codeaurora.org wrote:
> On 2021-08-12 18:39, Matthias Kaehlcke wrote:
> > On Thu, Aug 12, 2021 at 01:11:12PM +0530, Rajesh Patil wrote:
> > > From: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > 
> > > Add QSPI DT node and qspi_opp_table for SC7280 SoC.
> > > 
> > > Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 62
> > > ++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 62 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index 53a21d0..f8dd5ff 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -415,6 +415,25 @@
> > >  		method = "smc";
> > >  	};
> > > 
> > > +	qspi_opp_table: qspi-opp-table {
> > > +		compatible = "operating-points-v2";
> > > +
> > > +		opp-75000000 {
> > > +			opp-hz = /bits/ 64 <75000000>;
> > > +			required-opps = <&rpmhpd_opp_low_svs>;
> > > +		};
> > > +
> > > +		opp-150000000 {
> > > +			opp-hz = /bits/ 64 <150000000>;
> > > +			required-opps = <&rpmhpd_opp_svs>;
> > > +		};
> > > +
> > > +		opp-300000000 {
> > > +			opp-hz = /bits/ 64 <300000000>;
> > > +			required-opps = <&rpmhpd_opp_nom>;
> > > +		};
> > > +	};
> > > +
> > 
> > From v3:
> > 
> > roja> Can we move this "qspi_opp_table" to / from /soc?
> > 
> > bjorn> If you have made a proper attempt to convince Rob and Mark that
> > bjorn> a child "opp-table" in a SPI master is not a SPI device - and the
> > bjorn> conclusion is that this is not a good idea...then yes it should
> > live
> > bjorn> outside /soc.
> > 
> > I didn't see a follow up on this, was such an attempt made? Is there a
> > link to the discussion?
> 
> For now I am keeping qspi_opp_table  and qup_opp_table outside the SoC and
> posting V6.
> I will continue the discussion with DT folks and once concluded I will
> update as required.

Do you have a link to that discussion so that people can follow along or
chime in?