From: Andi Kleen <ak@suse.de>
To: "Chen, Kenneth W" <kenneth.w.chen@intel.com>
Subject: Re: [patch] speed up single bio_vec allocation
Date: Fri, 8 Dec 2006 05:37:11 +0100
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On Friday 08 December 2006 05:23, Chen, Kenneth W wrote:
> Andi Kleen wrote on Thursday, December 07, 2006 6:28 PM
> > "Chen, Kenneth W" <kenneth.w.chen@intel.com> writes:
> > > I tried to use cache_line_size() to find out the alignment of struct bio, but
> > > stumbled on that it is a runtime function for x86_64.
> > 
> > It's a single global variable access:
> > 
> > #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
> > 
> > Or do you mean it caused cache misses?  boot_cpu_data is cache aligned
> > and practically read only, so there shouldn't be any false sharing at least.
> 
> No, I was looking for a generic constant that describes cache line size.

The same kernel binary runs on CPUs with 
different cache line sizes. For example P4 has 128 bytes, Core2 64 bytes.

However there is a worst case alignment that is used for static
alignments which is L1_CACHE_BYTES. It would be normally 128 bytes
on a x86 kernel, unless it is especially compiled for a CPU with
a smaller cache line size.

-Andi
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