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From:   Hao Peng <flyingpenghao@gmail.com>
Date:   Tue, 7 Sep 2021 10:35:31 +0800
Message-ID: <CAPm50aLiB+O85mgcKcOZwO6J-DXjwK=p+7npBH-qVdkL-77Huw@mail.gmail.com>
Subject: Re: [PATCH] x86/tsx: clear RTM and HLE when MSR_IA32_TSX_CTRL is not supported
To:     Xiaoyao Li <xiaoyao.li@intel.com>
Cc:     Borislav Petkov <bp@alien8.de>, tglx@linutronix.de,
        mingo@redhat.com, x86@kernel.org, linux-kernel@vger.kernel.org,
        Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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On Tue, Sep 7, 2021 at 10:08 AM Xiaoyao Li <xiaoyao.li@intel.com> wrote:
>
> On 9/7/2021 9:47 AM, Hao Peng wrote:
> > On Mon, Sep 6, 2021 at 5:30 PM Borislav Petkov <bp@alien8.de> wrote:
> >>
> >> On Mon, Sep 06, 2021 at 10:46:05AM +0800, Hao Peng wrote:
> >>> If hypervisor does not support MSR_IA32_TSX_CTRL, but guest supports
> >>> RTM and HLE features, it will affect TAA mitigation.
> >>>
> >>> Signed-off-by: Peng Hao <flyingpeng@tencent.com>
> >>> ---
> >>>   arch/x86/kernel/cpu/tsx.c | 7 +++++++
> >>>   1 file changed, 7 insertions(+)
> >>>
> >>> diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
> >>> index 9c7a5f049292..5e852c14fef2 100644
> >>> --- a/arch/x86/kernel/cpu/tsx.c
> >>> +++ b/arch/x86/kernel/cpu/tsx.c
> >>> @@ -122,6 +122,13 @@ void __init tsx_init(void)
> >>>
> >>>          if (!tsx_ctrl_is_supported()) {
> >>>                  tsx_ctrl_state =3D TSX_CTRL_NOT_SUPPORTED;
> >>> +
> >>> +               /* If hypervisor does not support MSR_IA32_TSX_CTRL e=
mulation,
> >>> +                * but guest supports RTM and HLE features, it will a=
ffect TAA
> >>> +                * =EF=BC=88tsx_async_abort=EF=BC=89mitigation.
> >>> +                */
> >>> +               setup_clear_cpu_cap(X86_FEATURE_RTM);
> >>> +               setup_clear_cpu_cap(X86_FEATURE_HLE);
>
> anyway, IMHO, we shouldn't do anything here for TAA. It should be in
> taa_select_mitigation()
>
> >>>                  return;
> >>>          }
> >>
> >> How does that even happen - the hypervisor does not support the MSR bu=
t
> >> "guest supports" TSX features?!
> >>
> >> I guess the guest is detecting it wrong.
> >>
> >> What hypervisor, what guest, how do I reproduce?
> >>
> > hypervisor is kvm, guest is linux too.
> >> Please give full details.
> >>
> > The host I used is kernel-5.4, and guest is kernel-5.13.
> > MSR_IA32_TSX_CTRL is exposed
> > to guest and guest to support RTM and HLE features, no direct
> > dependence. at the qemu I
> > started guest with -cpu host-model.
> > I have viewed the code of kernel-5.4, and MSR_IA32_TSX_CTRL is not
> > exposed to guest.
>
> Does guest see TAA_NO bit?
>
Guest can't see taa_no, which requires updating qemu to solve. But I think
there is a compatibility process here.
> > Thanks.
> >> --
> >> Regards/Gruss,
> >>      Boris.
> >>
> >> https://people.kernel.org/tglx/notes-about-netiquette
>