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Date:   Mon, 6 Sep 2021 22:14:54 -0700
From:   Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To:     Hao Peng <flyingpenghao@gmail.com>
Cc:     tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/tsx: clear RTM and HLE when MSR_IA32_TSX_CTRL is not
 supported
Message-ID: <20210907051454.56eocxfxeuqixlf6@gupta-dev2.localdomain>
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On 06.09.2021 10:46, Hao Peng wrote:
>If hypervisor does not support MSR_IA32_TSX_CTRL, but guest supports
>RTM and HLE features, it will affect TAA mitigation.

Guests are on purpose not allowed to control TSX via MSR_IA32_TSX_CTRL,
otherwise a malicious guest can enable TSX and attack host or other
guests. The TAA mitigation within a guest is same as MDS i.e.
micro-architectural buffer clear using VERW instruction. Support for
VERW is added by the microcode update and enumerate by
MSR_ARCH_CAP[MD_CLEAR] bit. 

>Signed-off-by: Peng Hao <flyingpeng@tencent.com>
>---
> arch/x86/kernel/cpu/tsx.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
>diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
>index 9c7a5f049292..5e852c14fef2 100644
>--- a/arch/x86/kernel/cpu/tsx.c
>+++ b/arch/x86/kernel/cpu/tsx.c
>@@ -122,6 +122,13 @@ void __init tsx_init(void)
>
>        if (!tsx_ctrl_is_supported()) {
>                tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
>+
>+               /* If hypervisor does not support MSR_IA32_TSX_CTRL emulation,
>+                * but guest supports RTM and HLE features, it will affect TAA
>+                * （tsx_async_abort）mitigation.
>+                */
>+               setup_clear_cpu_cap(X86_FEATURE_RTM);
>+               setup_clear_cpu_cap(X86_FEATURE_HLE);

This is not correct. TSX feature can exist without TSX_CTRL MSR.
Moreover, clearing the cached bits with setup_clear_cpu_cap() doesn't
disable the TSX feature in CPU.

Thanks,
Pawan