Received: by 2002:a05:6a10:eb17:0:0:0:0 with SMTP id hx23csp3931969pxb; Tue, 7 Sep 2021 10:36:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxwbSnoI+8O68Po94/akkx8680ZU+Cx9J3+iYUuPAjBsjk/TtwZYdXPi38K2JsEsALaOTvr X-Received: by 2002:a50:99cc:: with SMTP id n12mr662606edb.53.1631036216265; Tue, 07 Sep 2021 10:36:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631036216; cv=none; d=google.com; s=arc-20160816; b=NtFjzizmxTQYw/odqrbbUM7yO75q9191e41wPQ1WZZCjkK8r/e7w1b8kd+wjY3VuxH nu8FT1R9S/OtjvBcGMEMG4OcJdE+Y5SHLpfWbYcDeSASJR1mxTasDtIJlkiFIkK5arMl XAFCr6EZjl64DCT0q9FNST80esjJh9jOtWn1TWIEedOmbzYq51lN4FknoD5K506x3y3t Nzjc+QpfvjHgB39gQujCTgS+1fDdKMeZpHHbA9WJ/aJBnJnmWVIgNVhCTD8aTypNOGdS 4xRdUM7nCvLYyCA5AeCyRrz9wjf9Zw7SMtkNhYSjZc58E5UPCTHiU17fX2BJDj80JaHt Clew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date; bh=1WBSoQr/r4Jf8WbqikrseoFRBYtb27Gx2gDXeUYlWc4=; b=GeQrzFKK/Wg3ARL2MckxFSUk+5xC2ZP969UOPBQyhnusUSmjZUr4PqtM0QM7Xec0fM ywEH/iJjXwt8SpaT1iE0ArM784xQp7JBZZEIzForZkFK1KcBxmHZK06KXprVD4XTFko3 2SqFOxBKxUUNpZ1+XODIl9Q7jzlDxuHYKxElQAeaY8dy0K2BfLTIqywwANYyFWUkBKR4 Q2ljgOREMpLxfSJE03OHNKOTBrLR7JsV67wHhfG3iF1vvE2D1Fa0cFlohJ48ybqCApsO b5Y8HVdBxe/t8XUfGxtsuvnCXT7i845yV3qzwZkvpS0O3xd2kkRvtb4z55rC5hNe7Tan eqhg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w7si8228124edc.560.2021.09.07.10.36.32; Tue, 07 Sep 2021 10:36:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343887AbhIGQg4 convert rfc822-to-8bit (ORCPT + 99 others); Tue, 7 Sep 2021 12:36:56 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:44485 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231378AbhIGQg4 (ORCPT ); Tue, 7 Sep 2021 12:36:56 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 93BC560009; Tue, 7 Sep 2021 16:35:46 +0000 (UTC) Date: Tue, 7 Sep 2021 18:35:45 +0200 From: Miquel Raynal To: Grygorii Strashko Cc: Roger Quadros , , , , , , , , , , Subject: Re: [PATCH v3 5/8] dt-bindings: mtd: ti,gpmc-nand: Convert to yaml Message-ID: <20210907183545.3e281b7d@xps13> In-Reply-To: References: <20210907113226.31876-1-rogerq@kernel.org> <20210907113226.31876-6-rogerq@kernel.org> <20210907160317.2ec5304a@xps13> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Grygorii, > > > >> + > >> + nand-bus-width: > >> + description: > >> + Bus width to the NAND chip > >> + $ref: /schemas/types.yaml#/definitions/uint32 > >> + enum: [8, 16] > >> + default: 8 > > > > This is part of nand-controller.yaml binding and should not be there. > > > >> + > >> +allOf: > >> + - $ref: "../memory-controllers/ti,gpmc-child.yaml" > > > > Maybe you need to reference the nand controller bindings as well > > > > This will not work out of the box :( as nand-controller.yaml defines both > nand controller and nand memory. It potentially might work if it will be possible to split > nand memory definition (or nand memory properties) out of and-controller.yaml, similarly to > ti,gpmc-child.yaml from this series. What you think would be the issue? I am not opposed to split nand-controller.yaml into nand-controller.yaml and nand-chip.yaml if it simplifies the description of controllers but I don't get why it would be needed. In particular since we expect all drivers to support the nand-controller { controller-props; nand-chip { chip-props; } } organization which has been enforced since at least 2018. Having a controller vs. chip representation is fundamentally right. But here I see how "legacy" are these bindings with so much unneeded specific "ti," properties... On one side it would be good to verify that the driver supports this representation (which I believe is true) and on the other side maybe it's time to advertise "better" bindings as well. Thanks, Miquèl