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[23.128.96.18]) by mx.google.com with ESMTP id p22si812330ejm.526.2021.09.07.20.47.01; Tue, 07 Sep 2021 20:47:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@telus.net header.s=google header.b=MVYKn+8U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=telus.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbhIHDoi (ORCPT + 99 others); Tue, 7 Sep 2021 23:44:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234220AbhIHDoh (ORCPT ); Tue, 7 Sep 2021 23:44:37 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A58C5C061757 for ; Tue, 7 Sep 2021 20:43:29 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id e23so2027520lfj.9 for ; Tue, 07 Sep 2021 20:43:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telus.net; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8B7rsR/U6MYIRRZ/pFi74UHxEXbdwK5SKXtNls19AwM=; b=MVYKn+8UHt/W4LnI54Pw8aJsZHCwL/RpcHVW56Gm/CN+qa21pJzbxJblhfXbDAzvJl ztR6wItASfyDw19FMLU1ym+MP3ITbCXen/Y4nf5/xXiRH8TWBq3y24uI9pI9u6+DCUdx CETtRRf48WWKqHLj0jcDOQLNPZI2xCiFQStDFF+h4/U33/m3UIg5Eq4/fvZUQCCJneNA 8VCWRzazXqBzxMtQyDUsu/0leR3FFG1KNVOiilKrEGqcIR+LuNAvTf/zqbs90ilGuugd nIDD1dgvZTPy5CTPUVTPHHH61C40WXoDmUAcKMSa0PdOVXr3D9dcPAHVub27vFhPskIi Evng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8B7rsR/U6MYIRRZ/pFi74UHxEXbdwK5SKXtNls19AwM=; b=pdQLLZfGrTow/+CqR55zm9rIC5IYmPvDW1uwYrKOFv4XW5QqQ3N5Kp4d/RDYAWWUyL KJ1PmblIjE1teWFH/R+buWEih0KDfwpXXYv0z/5EON9Aqgh4Q009RFDapSXjF9F6wdGs jSPqs9kHL+Syer/9+M0BgjpHYoio0bzmOI1ebVj9dsbbsxK/S9+OLTxSRbtJBF6RwnBO 8dednJ/dtV5ZwlZ/XPt8TwEfvn88C7VLM6+0rshsRRXmDK6pqFJtlz8cvJVKX3mL/xaE lvJC2zcqF2mRhrdm2VvRBk4rnaSnIyjTR4gdPW2DgAAGHMbZM7C1bWKm1FirA8S1DiFX OlSQ== X-Gm-Message-State: AOAM531Ponw1Imxlxaw97fzxCH5Bb+JWJbaG0JpkIfgBnkst6qtDy2y2 zhyR/REPMuDERy/twQwoI0EsH9cXGv3aUUngp4V89Q== X-Received: by 2002:ac2:5456:: with SMTP id d22mr1135144lfn.139.1631072607813; Tue, 07 Sep 2021 20:43:27 -0700 (PDT) MIME-Version: 1.0 References: <20210513132051.31465-1-ggherdovich@suse.cz> <067ee60e47a0350d01f0c3f216c1032818044b36.camel@suse.cz> <2a1b000cd101737400f6320ef18c0143d3a5145b.camel@linux.intel.com> <7abae13c235d74f4789cd93c6c6b0cbf69df243d.camel@linux.intel.com> In-Reply-To: <7abae13c235d74f4789cd93c6c6b0cbf69df243d.camel@linux.intel.com> From: Doug Smythies Date: Tue, 7 Sep 2021 20:43:19 -0700 Message-ID: Subject: Re: [PATCH v2] cpufreq: intel_pstate: Add Icelake servers support in no-HWP mode To: Srinivas Pandruvada Cc: Giovanni Gherdovich , "Rafael J . Wysocki" , Viresh Kumar , Len Brown , Linux PM list , Linux Kernel Mailing List , dsmythies Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 7, 2021 at 7:04 PM Srinivas Pandruvada wrote: > > On Tue, 2021-09-07 at 13:16 -0700, Doug Smythies wrote: > > Hi Srinivas, Thank you for your reply. > > > > On Tue, Sep 7, 2021 at 9:01 AM Srinivas Pandruvada > > wrote: > > > On Tue, 2021-09-07 at 08:45 -0700, Doug Smythies wrote: > > > > > > > > Recent ASUS BIOS updates have changed the default system > > > > response for this old thread, rendering "intel_pstate=no_hwp" > > > > useless. > > > > > > > > It also raises a question: If BIOS has forced HWP, then how do we > > > > prevent the acpi-cpufreq driver from being used? Read on. > > > > > > Does BIOS has option to enable Intel speed shift with no legacy > > > support? > > > Then this option will not populate ACPI _PSS table. > > > > The option is there no matter what. > > I have tried every variation of legacy or no legacy that > > I can find. Currently: > > Current boot mode: UEFI Firmware mode > > SecureBoot: disabled > > > > > > > > > > > > > On Fri, May 14, 2021 at 3:12 PM Doug Smythies < > > > > dsmythies@telus.net> > > > > wrote: > > > > > > > > > > On Fri, May 14, 2021 at 1:33 PM Giovanni Gherdovich < > > > > > ggherdovich@suse.cz> wrote: > > > > > > On Fri, 2021-05-14 at 08:31 -0700, Doug Smythies wrote: > > > > ... > > > > > > > > ... > > > > Previous correspondence was with BIOS version 1003. There have > > > > been 3 > > > > BIOS > > > > releases since then (at least that I know of), 2103, 2201, 2301, > > > > and > > > > all of them > > > > have changed the behaviour of the "Auto" setting for Intel Speed > > > > Shift > > > > Technology BIOS setting, forcing it on upon transfer of control > > > > to > > > > the OS. > > > > > > > > Where with "intel_pstate=no_hwp" one used to get 0 for > > > > MSR_PM_ENABLE > > > > (0x770) they now get 1. > > > > > > So they are forcing Out of band OOB mode. > > > Does bit 8 or 18 in MSR 0x1aa is set? > > > > No. > > So there is no legacy path. I think you are working with their support. Yes, for almost a month now, with very little to show for it. We'll see what happens. I did get a message this afternoon: "Our GTSD is debugging the issue,. When they have the result, they will directly update you." > In HWP mode does setting scaling min/max frequency has any impact? No. I wouldn't have expected it to, as the system is confused as to who is in charge. The acpi-cpufreq driver thinks it is in charge, but HWP thinks it is. The intel_pstate driver works fine. ... Doug > > Thanks, > Srinivas > > > > > Here is the output from my msr reader/decoder program. > > Kernel 5.14 (unpatched). > > intel_pstate=disable > > BIOS setting "Auto" for Intel Speed Shift, > > Driver: acpi-cpufreq > > > > doug@s19:~$ sudo c/msr-decoder > > How many CPUs?: 12 > > 8.) 0x198: IA32_PERF_STATUS : CPU 0-11 : 45 : 45 : 45 : 45 : > > 45 : 45 : 45 : 45 : 45 : 45 : 45 : 45 : > > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable > > 1.) 0x19C: IA32_THERM_STATUS: 88450000 > > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination > > enabled > > OOB Bit 8 reset OOB Bit 18 reset > > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88410000 > > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0 > > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO > > disable > > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 10B2930 : high 48 : > > guaranteed 41 : efficient 11 : lowest 1 > > 6.) 0x774: IA32_HWP_REQUEST: CPU 0-11 : > > raw: 80003001 : 80003001 : 80003001 : 80003001 : 80003001 : > > 80003001 : 80003001 : 80003001 : 80003001 : 80003001 : 80003001 : > > 80003001 : > > min: 1 : 1 : 1 : 1 : 1 : > > 1 : 1 : 1 : 1 : 1 : 1 : 1 : > > max: 48 : 48 : 48 : 48 : 48 : > > 48 : 48 : 48 : 48 : 48 : 48 : 48 > > : > > des: 0 : 0 : 0 : 0 : 0 : > > 0 : 0 : 0 : 0 : 0 : 0 : 0 : > > epp: 128 : 128 : 128 : 128 : 128 : > > 128 : 128 : 128 : 128 : 128 : 128 : 128 > > : > > act: 0 : 0 : 0 : 0 : 0 : > > 0 : 0 : 0 : 0 : 0 : 0 : 0 : > > 7.) 0x777: IA32_HWP_STATUS: 0 : high 0 : guaranteed 0 : efficient 0 : > > lowest 0 > > > > ... > > > > ... Doug > >