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Wed, 8 Sep 2021 05:06:36 +0000 From: ChiaWei Wang To: Rob Herring CC: "joel@jms.id.au" , "andrew@aj.id.au" , "lee.jones@linaro.org" , "osk@google.com" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" Subject: RE: [PATCH v2 1/3] dt-bindings: aspeed-lpc: Add UART routing compatible string Thread-Topic: [PATCH v2 1/3] dt-bindings: aspeed-lpc: Add UART routing compatible string Thread-Index: AQHXn6EXTrG9luH4/kKvLz7wmMPMC6uY8jOAgACs7OA= Date: Wed, 8 Sep 2021 05:06:35 +0000 Message-ID: References: <20210902021817.17506-1-chiawei_wang@aspeedtech.com> <20210902021817.17506-2-chiawei_wang@aspeedtech.com> In-Reply-To: Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9d1e49ef-7ae3-4636-2251-08d972866f40 x-ms-traffictypediagnostic: HK2PR06MB3252: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3631; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: HK0PR06MB3779.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d1e49ef-7ae3-4636-2251-08d972866f40 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Sep 2021 05:06:36.4355 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: n/8xUaMoBZVk0q4kifuz58bd+MkzAXxvOm1Xdd/4agWezfFuAOdUJ9+Z/xcekspmyTJrIqS0YKD+/vL3JWF65QHPUdvCK5INFTZmqs4K0bo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR06MB3252 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Rob Herring > Sent: Wednesday, September 8, 2021 2:47 AM >=20 > On Thu, Sep 02, 2021 at 10:18:14AM +0800, Chia-Wei Wang wrote: > > Add the compatible string and the device tree description for the > > Aspeed AST25xx/AST26xx UART routing control. > > > > Signed-off-by: Chia-Wei Wang > > --- > > .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 +++++++++++++++++++ > > 1 file changed, 22 insertions(+) >=20 > Either convert aspeed-lpc.txt to DT schema or make this a separate schema > doc. I will send a v3 patch with a separate schema included. Thanks. Chiawei >=20 > > > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > index 936aa108eab4..45d44f812e5e 100644 > > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > > @@ -155,3 +155,25 @@ lpc_reset: reset-controller@98 { > > reg =3D <0x98 0x4>; > > #reset-cells =3D <1>; > > }; > > + > > +UART routing control > > +-------------------- > > + > > +The UART routing control manages the RX muxes among the UART > > +controllers and the I/O pins. This is typicall used for the > > +Serial-Over-Lan (SOL) service. > > + > > +Required properties: > > + > > + - compatible: One of: > > + "aspeed,ast2500-uart-routing"; > > + "aspeed,ast2600-uart-routing"; > > + > > + - reg: offset and length of the IP in the LPC memory region > > + > > +Example: > > + > > +uart_routing: uart-routing@98 { > > + compatible =3D "aspeed,ast2600-uart-routing"; > > + reg =3D <0x98 0x8>; > > +}; > > -- > > 2.17.1 > > > >