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From:   Chester Lin <clin@suse.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Larisa Grigore <larisa.grigore@nxp.com>,
        Radu Nicolae Pirea <radu-nicolae.pirea@oss.nxp.com>,
        =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>,
        Matthias Brugger <mbrugger@suse.com>
CC:     s32@nxp.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-serial@vger.kernel.org,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com,
        bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com,
        ghennadi.procopciuc@nxp.com, "Ivan T . Ivanov" <iivanov@suse.de>,
        "Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support
Date:   Wed,  8 Sep 2021 14:45:25 +0800
Message-ID: <20210908064528.922-6-clin@suse.com>
In-Reply-To: <20210908064528.922-1-clin@suse.com>
References: <20210908064528.922-1-clin@suse.com>
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Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add new Signed-off-by.
- Fix the copyright string.
- Remove aliases.
- Revise reg properties based on new cell size.

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts=
/freescale/s32g2.dtsi
index 53b18671deec..59ea8a25aa4c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,6 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2017-2021 NXP
  */
=20
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -84,6 +85,30 @@ soc {
 		#size-cells =3D <1>;
 		ranges =3D <0 0 0 0x80000000>;
=20
+		uart0: serial@401c8000 {
+			compatible =3D "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0x401c8000 0x3000>;
+			interrupts =3D <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
+		uart1: serial@401cc000 {
+			compatible =3D "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0x401cc000 0x3000>;
+			interrupts =3D <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
+		uart2: serial@402bc000 {
+			compatible =3D "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg =3D <0x402bc000 0x3000>;
+			interrupts =3D <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status =3D "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible =3D "arm,gic-v3";
 			reg =3D <0x50800000 0x10000>,
--=20
2.30.0