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Message-ID: <9929d2390612081538w4fd8ab4j23b05ed30f48060a@mail.gmail.com>
Date: Fri, 8 Dec 2006 15:38:54 -0800
From: "Jeff Kirsher" <jeffrey.t.kirsher@intel.com>
To: "Auke Kok" <auke-jan.h.kok@intel.com>
Subject: Re: [PATCH 2/6] e1000: use pcix_set_mmrbc
Cc: "Stephen Hemminger" <shemminger@osdl.org>,
       "Roland Dreier" <rdreier@cisco.com>,
       "Greg Kroah-Hartman" <gregkh@suse.de>,
       linux-pci@atrey.karlin.mff.cuni.cz, linux-kernel@vger.kernel.org,
       "Cramer, Jeb J" <jeb.j.cramer@intel.com>
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	 <20061208182500.478856000@osdl.org> <adalkli6p0e.fsf@cisco.com>
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On 12/8/06, Auke Kok <auke-jan.h.kok@intel.com> wrote:
> Stephen Hemminger wrote:
> > On Fri, 08 Dec 2006 13:45:05 -0800
> >
> > Hmm.. looks like all that code should really be moved off to PCI bus
> > quirk/setup.  None of it is E1000 specific.  Something like this (untested):
>
> This is not true, and I have to NAK the original patch. Part of the code Stephan is
> removing fixes a BUG in one of our *e1000 parts* that has the wrong size.
>
> It would be nice to fix generix pci-x issues qith quirks for platforms but the
> adjustment needs to stay for this specific e1000 case.
>
> Perhaps we can accomodate that specific case so that it is apparent from our code, as is
> not the case right now.
>
> Auke
>
> PS Thanks to Jeb for fishing this out ;)
>

Actually there are two issues that are being resolved with this function:
1- BIOS reports incorrect maximum memory read byte count (mmrbc).
This was seen on some older systems > 5 years ago.

2- EEPROM is reporting an incorrect mmrbc.

This function corrects both of these issues, Stephen second suggestion
of moving the BIOS fix to quirks.c is fine with me.  Even with the
code added to quirks.c, we still need this workaround as is to correct
for EEPROM's reporting 4k for a mmrbc.  So I am fine with Stephen's
second suggestion NAK the suggested change to e1000_hw.c

-- 
Cheers,
Jeff
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