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Wed, 8 Sep 2021 10:18:35 +0000 From: ChiaWei Wang To: Paul Fertser CC: "robh+dt@kernel.org" , "joel@jms.id.au" , "andrew@aj.id.au" , "lee.jones@linaro.org" , "osk@google.com" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , Konstantin Klubnichkin Subject: RE: [PATCH v2 0/3] arm: aspeed: Add UART routing support Thread-Topic: [PATCH v2 0/3] arm: aspeed: Add UART routing support Thread-Index: AQHXn6Ep4pfNy4cUzEmFUBdsNZd0kquZ7IKAgAAENXA= Date: Wed, 8 Sep 2021 10:18:35 +0000 Message-ID: References: <20210902021817.17506-1-chiawei_wang@aspeedtech.com> <20210908094248.GZ23326@home.paul.comp> In-Reply-To: <20210908094248.GZ23326@home.paul.comp> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=none action=none header.from=aspeedtech.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: HK0PR06MB3779.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41af0b3a-687c-41ab-b21b-08d972b2049f X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Sep 2021 10:18:35.5366 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: VtS8BfG7ayM6KNsukgyfo8Dct0qYQT1b9nQR1naJLYpnPcRokZ4Agp2YEkdctf/GbLEn+kziEpp+WxIana1+G3TkpoA+Pc5no3Mx0Fo/9ow= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR06MB3556 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Paul, > From: Paul Fertser > Sent: Wednesday, September 8, 2021 5:43 PM >=20 > Hello, >=20 > On Thu, Sep 02, 2021 at 10:18:13AM +0800, Chia-Wei Wang wrote: > > Add UART routing driver and the device tree nodes. >=20 > Thank you for working on exposing this functionality in upstreamable way, > that's so much better than all the register-level hacks in U-Boot and sim= ilar > approaches! >=20 >=20 > One (somewhat) related question that I hope you do not mind answering: > is there anything special regarding the routing or other configuration th= at > needs to be done for VUART to work with IRQs? No. The routing control has no relation to VUART. >=20 > The reason I ask is that I have tried hard (and I know several other deve= lopers > who have too) to use VUART functionality but somehow as soon as Linux was > booting on host and starting to use the IRQ-based > 16550 driver the communication was halted both ways. Basically, the BMC > firmware was enabling VUART in DTS, then setting LPC address to > 0x3F8 and LPC IRQ to 4 and reading/writing using the corresponding > /dev/ttyS* node. The datasheet is not clearly telling what other actions = need to > be performed for this to work. Not using VUART and instead routing UART1 > lines with exactly the same pinctrl/pinmux worked just fine. One detail i= s that > with VUART the host wasn't seeing new interrupts but when they were > simulated by exporting the LPC interrupt pin via /sys/class/gpio and togg= ling it > manually the data was getting through. >=20 > Does UART1 need some explicit disabling for VUART IRQs to work? It looks = like > setting LPC address and IRQ number in VUART is enough to override the > register part but probably not for the interrupt? You may need to confirm that the Host does not enable the SIO SUART1 device= . This will conflict with VUART as both SUART and VAURT are competing for the= port address 0x3f8 and SIRQ 4. >=20 > -- > Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! > mailto:fercerpav@gmail.com