Received: by 2002:a05:6a10:eb17:0:0:0:0 with SMTP id hx23csp711991pxb; Wed, 8 Sep 2021 10:29:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYr3qWpnEwXdxcKBwK97wD55g5F5fu6BNtZAXd3yB2A9MsDJUCfGB/NtVFOqinpcdekPHj X-Received: by 2002:a6b:c1:: with SMTP id 184mr876996ioa.48.1631122186617; Wed, 08 Sep 2021 10:29:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631122186; cv=none; d=google.com; s=arc-20160816; b=WPsX7SUMeh85UKw25+cBaa9T3k/2/W/UwdeuJENfMQoKO2dU00bYDX0OCh0CPZhYAi MKW4wq60SKQy73/WqGDKutB0A1cttRhz15WtRjJdDiqtuBKFjrLxyDjaGkcZIXKIzp/i TfypLFQziyrl9wSepR0ynEE+lVOREqMIr3mVV/RHHuoXsqidT4DzIgyXW7A2Lr3J27Qf s7Fc/Xbr8N4M4jGOPbpGXdGwAO+VnyN3AyWAPClfgHt8Stvf8DSkQzzRmauD0c9b0MtE W7dC4oTxYME76JEv5XSAWpO0NtTmYehGzprSNBMHgxiB1P3Z9Jj93+K6PtO3fiQfNMOp tiNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:subject:cc:to:from:date; bh=8WbqGam9//qM+6PaYuCYyz8ygwWk3SNt7O5ZlmPlFC4=; b=dvEmjBeEGfi/qflIDG/Qp9brU4ey0jWiSD7bfD1u0e3eetAA32j4Q4OiOLCGmBckjz PC0sekdFbSo03aqg1R5UqF3R9qW7bsXn05mH0I56qaJpWOWjau1O8GG6z/eLgNnOSY/G 5ttO4AVGFlSQxa28aUSRMFAJ7FlfTcGJEYKQ8ZwhiSlVYRTnzZQLnJmWCWITlZcIVPPG YvC3TyqO+MGSHfBvvF5+1r6dC2vvUXKPdGnD9QI9G4JeH9dzFuIbsTcL1vg+psyTgx++ yBppkK2udNjOn6h/bJm7MglWh5SisW/l50xdUqGOca5ZrIP8UVrDzGjywV6mwLH5v+wM x/Dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u20si2550700jao.113.2021.09.08.10.29.20; Wed, 08 Sep 2021 10:29:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352455AbhIHR2z (ORCPT + 99 others); Wed, 8 Sep 2021 13:28:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:60192 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbhIHR2y (ORCPT ); Wed, 8 Sep 2021 13:28:54 -0400 Received: from jic23-huawei (cpc108967-cmbg20-2-0-cust86.5-4.cable.virginm.net [81.101.6.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0F19A60EBA; Wed, 8 Sep 2021 17:27:39 +0000 (UTC) Date: Wed, 8 Sep 2021 18:31:05 +0100 From: Jonathan Cameron To: Fabrice Gasnier Cc: William Breathitt Gray , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v16 01/14] counter: stm32-lptimer-cnt: Provide defines for clock polarities Message-ID: <20210908183105.062869dd@jic23-huawei> In-Reply-To: References: X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 31 Aug 2021 15:38:50 +0200 Fabrice Gasnier wrote: > On 8/27/21 5:47 AM, William Breathitt Gray wrote: > > The STM32 low-power timer permits configuration of the clock polarity > > via the LPTIMX_CFGR register CKPOL bits. This patch provides > > preprocessor defines for the supported clock polarities. > > > > Cc: Fabrice Gasnier > > Signed-off-by: William Breathitt Gray > > --- > > drivers/counter/stm32-lptimer-cnt.c | 6 +++--- > > include/linux/mfd/stm32-lptimer.h | 5 +++++ > > 2 files changed, 8 insertions(+), 3 deletions(-) > > Hi William, > > You can add my: > Reviewed-by: Fabrice Gasnier Applied to the togreg branch of iio.git and push out as testing for all the normal reasons > > Thanks, > Fabrice > > > > > diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c > > index 13656957c45f..7367f46c6f91 100644 > > --- a/drivers/counter/stm32-lptimer-cnt.c > > +++ b/drivers/counter/stm32-lptimer-cnt.c > > @@ -140,9 +140,9 @@ static const enum counter_function stm32_lptim_cnt_functions[] = { > > }; > > > > enum stm32_lptim_synapse_action { > > - STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE, > > - STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE, > > - STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES, > > + STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE = STM32_LPTIM_CKPOL_RISING_EDGE, > > + STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE = STM32_LPTIM_CKPOL_FALLING_EDGE, > > + STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES = STM32_LPTIM_CKPOL_BOTH_EDGES, > > STM32_LPTIM_SYNAPSE_ACTION_NONE, > > }; > > > > diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h > > index 90b20550c1c8..06d3f11dc3c9 100644 > > --- a/include/linux/mfd/stm32-lptimer.h > > +++ b/include/linux/mfd/stm32-lptimer.h > > @@ -45,6 +45,11 @@ > > #define STM32_LPTIM_PRESC GENMASK(11, 9) > > #define STM32_LPTIM_CKPOL GENMASK(2, 1) > > > > +/* STM32_LPTIM_CKPOL */ > > +#define STM32_LPTIM_CKPOL_RISING_EDGE 0 > > +#define STM32_LPTIM_CKPOL_FALLING_EDGE 1 > > +#define STM32_LPTIM_CKPOL_BOTH_EDGES 2 > > + > > /* STM32_LPTIM_ARR */ > > #define STM32_LPTIM_MAX_ARR 0xFFFF > > > >