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Wysocki" , Viresh Kumar , Shuah Khan , Borislav Petkov , Ingo Molnar , linux-pm@vger.kernel.org Cc: Deepak Sharma , Alex Deucher , Mario Limonciello , Jinzhou Su , Xiaojian Du , linux-kernel@vger.kernel.org, x86@kernel.org References: <20210908150001.3702552-1-ray.huang@amd.com> <20210908150001.3702552-4-ray.huang@amd.com> From: "Fontenot, Nathan" Message-ID: <53962105-07cb-d964-28d0-1cc4d2e7fe8b@amd.com> Date: Wed, 8 Sep 2021 14:14:37 -0500 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 In-Reply-To: <20210908150001.3702552-4-ray.huang@amd.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN7PR04CA0019.namprd04.prod.outlook.com (2603:10b6:806:f2::24) To SN6PR12MB4720.namprd12.prod.outlook.com (2603:10b6:805:e6::31) MIME-Version: 1.0 Received: from [172.31.130.72] (165.204.78.25) by SN7PR04CA0019.namprd04.prod.outlook.com (2603:10b6:806:f2::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; 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> > +/** > + * cppc_set_enable - Set to enable CPPC register. > + * @cpu: CPU for which to enable CPPC register. > + * @enable: enable field to write into share memory. > + * > + * Return: 0 for success, -ERRNO otherwise. > + */ > +int cppc_set_enable(int cpu, u32 enable) > +{ > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); > + struct cpc_register_resource *enable_reg; > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); > + struct cppc_pcc_data *pcc_ss_data = NULL; > + int ret = -1; > + > + if (!cpc_desc) { > + pr_debug("No CPC descriptor for CPU:%d\n", cpu); > + return -ENODEV; > + } > + > + enable_reg = &cpc_desc->cpc_regs[ENABLE]; > + > + if (CPC_IN_PCC(enable_reg)) { > + > + if (pcc_ss_id < 0) > + return -EIO; > + > + ret = cpc_write(cpu, enable_reg, enable); > + if (ret) > + return ret; > + > + pcc_ss_data = pcc_data[pcc_ss_id]; > + > + down_write(&pcc_ss_data->pcc_lock); > + send_pcc_cmd(pcc_ss_id, CMD_WRITE); Shouldn't we be checking the return value from send_pcc_cmd()? Also, if the call to send_pcc_cmd() fails do we need to update enable_reg? i.e. cpc_write(..., !enable); -Nathan > + up_write(&pcc_ss_data->pcc_lock); > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(cppc_set_enable); > + > /** > * cppc_set_perf - Set a CPU's performance controls. > * @cpu: CPU for which to set performance controls. > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h > index 9f4985b4d64d..3fdae40a75fc 100644 > --- a/include/acpi/cppc_acpi.h > +++ b/include/acpi/cppc_acpi.h > @@ -137,6 +137,7 @@ struct cppc_cpudata { > extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); > extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); > extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); > +extern int cppc_set_enable(int cpu, u32 enable); > extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); > extern bool acpi_cpc_valid(void); > extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data); > @@ -157,6 +158,10 @@ static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) > { > return -ENOTSUPP; > } > +static inline int cppc_set_enable(int cpu, u32 enable) > +{ > + return -ENOTSUPP; > +} > static inline int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps) > { > return -ENOTSUPP; > -- > 2.25.1 >