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[23.128.96.18]) by mx.google.com with ESMTP id l15si683253ios.94.2021.09.08.21.46.11; Wed, 08 Sep 2021 21:46:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@mg.codeaurora.org header.s=smtp header.b=gIAPpoWp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350436AbhIIEpo (ORCPT + 99 others); Thu, 9 Sep 2021 00:45:44 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:35042 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231284AbhIIEpn (ORCPT ); Thu, 9 Sep 2021 00:45:43 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1631162675; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=86NO7303RnnqVCGvNO9Xd0Q/tVu0MvKObILgGrslNnU=; b=gIAPpoWpmVDZqqHwe0MoIWL2y9BfpYEft4KepIn/JXB8r8Sksk8ENOVwMKsFxxLatDnMHx6A i55eKt3k1U07VP4Xa9lLZvaERDlgw+JHtrDEQeGE1yFQl66+bcNU8dM339H4incdlrtQYFGG vWub9i1cD6ezlmKiCp2+mxyajdE= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 61399123e34848cb6aa8c7ce (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 09 Sep 2021 04:44:19 GMT Sender: rajpat=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5E4B0C43617; Thu, 9 Sep 2021 04:44:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rajpat) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3D3D7C43460; Thu, 9 Sep 2021 04:44:18 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 09 Sep 2021 10:14:18 +0530 From: rajpat@codeaurora.org To: Matthias Kaehlcke Cc: Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com, skakit@codeaurora.org, sboyd@kernel.org, dianders@chromium.org, Roja Rani Yarubandi Subject: Re: [PATCH V7 6/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes In-Reply-To: References: <1630643340-10373-1-git-send-email-rajpat@codeaurora.org> <1630643340-10373-7-git-send-email-rajpat@codeaurora.org> Message-ID: X-Sender: rajpat@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-09-03 22:52, Matthias Kaehlcke wrote: > On Fri, Sep 03, 2021 at 09:58:59AM +0530, Rajesh Patil wrote: >> From: Roja Rani Yarubandi >> >> Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. >> >> Signed-off-by: Roja Rani Yarubandi >> Signed-off-by: Rajesh Patil >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 709 >> +++++++++++++++++++++++++++++++++++ >> 1 file changed, 709 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 32d1354..8fe54bf 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> + qup_spi8_data_clk: qup-spi8-data-clk { >> + pins = "gpio32", "gpio33", "gpio34"; >> + function = "qup10"; >> + }; >> + >> + qup_spi8_cs: qup-spi8-cs { >> + pins = "gpio35"; >> + function = "qup10"; >> + }; > > As for wrapper_0, I think we still want the nodes to configure the CS > as GPIO. > > If there are no other reasons to re-spin these could be added with a > follow-up > patch, so: > shall we add all removed qup_spiN_cs_gpio nodes? > Reviewed-by: Matthias Kaehlcke