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Date:   Thu, 9 Sep 2021 17:50:04 +0800
From:   Huang Rui <ray.huang@amd.com>
To:     "Fontenot, Nathan" <Nathan.Fontenot@amd.com>
CC:     "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Shuah Khan <skhan@linuxfoundation.org>,
        "Borislav Petkov" <bp@suse.de>, Ingo Molnar <mingo@kernel.org>,
        "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
        "Sharma, Deepak" <Deepak.Sharma@amd.com>,
        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "Limonciello, Mario" <Mario.Limonciello@amd.com>,
        "Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
        "Du, Xiaojian" <Xiaojian.Du@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 03/19] ACPI: CPPC: add cppc enable register function
Message-ID: <20210909094946.GB3702717@hr-amd>
References: <20210908150001.3702552-1-ray.huang@amd.com>
 <20210908150001.3702552-4-ray.huang@amd.com>
 <53962105-07cb-d964-28d0-1cc4d2e7fe8b@amd.com>
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On Thu, Sep 09, 2021 at 03:14:37AM +0800, Fontenot, Nathan wrote:
> On 9/8/2021 9:59 AM, Huang Rui wrote:
> > From: Jinzhou Su <Jinzhou.Su@amd.com>
> > 
> > Export the cppc enable register function for future use.
> > 
> > Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/acpi/cppc_acpi.c | 42 ++++++++++++++++++++++++++++++++++++++++
> >  include/acpi/cppc_acpi.h |  5 +++++
> >  2 files changed, 47 insertions(+)
> > 
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > index a4d4eebba1da..de4b30545215 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -1220,6 +1220,48 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
> >  }
> >  EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> >  
> > +/**
> > + * cppc_set_enable - Set to enable CPPC register.
> > + * @cpu: CPU for which to enable CPPC register.
> > + * @enable: enable field to write into share memory.
> > + *
> > + * Return: 0 for success, -ERRNO otherwise.
> > + */
> > +int cppc_set_enable(int cpu, u32 enable)
> > +{
> > +	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > +	struct cpc_register_resource *enable_reg;
> > +	struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > +	struct cppc_pcc_data *pcc_ss_data = NULL;
> > +	int ret = -1;
> > +
> > +	if (!cpc_desc) {
> > +		pr_debug("No CPC descriptor for CPU:%d\n", cpu);
> > +		return -ENODEV;
> > +	}
> > +
> > +	enable_reg = &cpc_desc->cpc_regs[ENABLE];
> > +
> > +	if (CPC_IN_PCC(enable_reg)) {
> > +
> > +		if (pcc_ss_id < 0)
> > +			return -EIO;
> > +
> > +		ret = cpc_write(cpu, enable_reg, enable);
> > +		if (ret)
> > +			return ret;
> > +
> > +		pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > +		down_write(&pcc_ss_data->pcc_lock);
> > +		send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> 
> Shouldn't we be checking the return value from send_pcc_cmd()?
> 
> Also, if the call to send_pcc_cmd() fails do we need to update
> enable_reg? i.e. cpc_write(..., !enable);
> 

Sounds reasonable. I will modify this in V2.

Thanks,
Ray