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[23.128.96.18]) by mx.google.com with ESMTP id gb5si1343212ejc.310.2021.09.09.03.32.44; Thu, 09 Sep 2021 03:33:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233654AbhIIKbX (ORCPT + 99 others); Thu, 9 Sep 2021 06:31:23 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:62891 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233820AbhIIKbC (ORCPT ); Thu, 9 Sep 2021 06:31:02 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 189A9irg075151; Thu, 9 Sep 2021 18:09:45 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 9 Sep 2021 18:29:14 +0800 From: Chia-Wei Wang To: , , , , , , , CC: , Subject: [PATCH v3 3/3] ARM: dts: aspeed: Add uart routing to device tree Date: Thu, 9 Sep 2021 18:29:07 +0800 Message-ID: <20210909102907.32037-4-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210909102907.32037-1-chiawei_wang@aspeedtech.com> References: <20210909102907.32037-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 189A9irg075151 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft Signed-off-by: Chia-Wei Wang Tested-by: Lei YU --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index c5aeb3cf3a09..b313a1cf5f73 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -383,6 +383,12 @@ interrupts = <8>; status = "disabled"; }; + + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2400-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; }; uart2: serial@1e78d000 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 73ca1ec6fc24..c7049454c7cb 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -491,6 +491,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@9c { + compatible = "aspeed,ast2500-uart-routing"; + reg = <0x9c 0x4>; + status = "disabled"; + }; + lhc: lhc@a0 { compatible = "aspeed,ast2500-lhc"; reg = <0xa0 0x24 0xc8 0x8>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 1b47be1704f8..cdc59c5d86fe 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -551,6 +551,12 @@ #reset-cells = <1>; }; + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + status = "disabled"; + }; + ibt: ibt@140 { compatible = "aspeed,ast2600-ibt-bmc"; reg = <0x140 0x18>; -- 2.17.1