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From:   Luming Yu <luming.yu@gmail.com>
Date:   Thu, 9 Sep 2021 18:34:40 +0800
Message-ID: <CAJRGBZyQuQohbf8v3H19zo1mpbvDXrbNVXCJAUpCEmHgmqTYpg@mail.gmail.com>
Subject: Re: [PATCH] perf: optimize clear page in Intel specified model with
 movq instruction
To:     Borislav Petkov <bp@alien8.de>
Cc:     Jinhua Wu <wujinhua@linux.alibaba.com>,
        "the arch/x86 maintainers" <x86@kernel.org>,
        zelin.deng@linux.alibaba.com, jiayu.ni@linux.alibaba.com,
        Andi Kleen <ak@linux.intel.com>,
        Luming Yu <luming.yu@intel.com>, fan.du@intel.com,
        artie.ding@linux.alibaba.com, "Luck, Tony" <tony.luck@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>,
        pawan.kumar.gupta@linux.intel.com,
        "Yu, Fenghua" <fenghua.yu@intel.com>,
        "H. Peter Anvin" <hpa@zytor.com>,
        ricardo.neri-calderon@linux.intel.com,
        Peter Zijlstra <peterz@infradead.org>
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On Thu, Sep 9, 2021 at 5:41 PM Borislav Petkov <bp@alien8.de> wrote:
>
> On Thu, Sep 09, 2021 at 04:45:51PM +0800, Jinhua Wu wrote:
> > Clear page is the most time-consuming procedure in page fault handling.
> > Kernel use fast-string instruction to clear page. We found that in specified
> > Intel model such as CPX and ICX, the movq instruction perform much better
> > than fast-string instruction when corresponding page is not in cache.
> > But when the page is in cache, fast string perform better. We show the test
> > result in the following:
>
> What you should do is show the extensive tests you've run with
> real-world benchmarks where you really can show 40% performance
> improvement.
>
> Also, the static branch "approach" you're using ain't gonna happen. If
> anything, another X86_FEATURE_* bit.

do you mean jump label would not be replaced to nop when its key is enabled?
so we could not use it in certain functions?
I don't understand exactly what "ain't  gonna happen"
>
> Good luck.
>
> --
> Regards/Gruss,
>     Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette