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[23.128.96.18]) by mx.google.com with ESMTP id h5si1602075ede.570.2021.09.09.04.52.15; Thu, 09 Sep 2021 04:52:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=GfJ9Y3+8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239329AbhIILtt (ORCPT + 99 others); Thu, 9 Sep 2021 07:49:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:47118 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239647AbhIILrk (ORCPT ); Thu, 9 Sep 2021 07:47:40 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 0C1F56124A; Thu, 9 Sep 2021 11:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1631187793; bh=vpGN6M9N/+VFlJTwRXh9c32T/+9r1GIZGJlU8Oq/aBk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GfJ9Y3+84PYYEXYbg7CrrZE1/WmC95rBxAAEXbjAg0VjBgZMfcJcKtiyG6E/uK/rZ ymEDTCKgMELwNKR0ezN1FUaIn7RGZliJNa7WnEsbDWufkFlUweiTVHaFjI065D6h8N lHLLAdFCeQNs3Tq8Mhz/S4ISG1Zp5UYuxwPTe5B8nh/8970CPCngT0CMGt3of24NIP Js4D1jMV2F+MODaX1izuXbfG2IVfHPVvs04nCMsWtUI5kcyIJt7xfR8aLPAgrnyhDy KcpMfg2eH33XkqPaDJjew5MbrG9dAhEd3DegwvEtFCwJ+bMiSW6UK7le9rRwDJycGA 4SIVxVrwNdAmA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Vidya Sagar , Jon Hunter , Thierry Reding , Sasha Levin , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH AUTOSEL 5.14 099/252] arm64: tegra: Fix Tegra194 PCIe EP compatible string Date: Thu, 9 Sep 2021 07:38:33 -0400 Message-Id: <20210909114106.141462-99-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210909114106.141462-1-sashal@kernel.org> References: <20210909114106.141462-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vidya Sagar [ Upstream commit bf2942a8b7c38e8cc2d5157b4f0323d7f4e5ec71 ] The initialization sequence performed by the generic platform driver pcie-designware-plat.c for a DWC based implementation doesn't work for Tegra194. Tegra194 has a different initialization sequence requirement which can only be satisfied by the Tegra194 specific platform driver pcie-tegra194.c. So, remove the generic compatible string "snps,dw-pcie-ep" from Tegra194's endpoint controller nodes. Signed-off-by: Vidya Sagar Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5ba7a4519b95..c8250a3f7891 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2122,7 +2122,7 @@ pcie@141a0000 { }; pcie_ep@14160000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ @@ -2162,7 +2162,7 @@ pcie_ep@14160000 { }; pcie_ep@14180000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ @@ -2202,7 +2202,7 @@ pcie_ep@14180000 { }; pcie_ep@141a0000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ -- 2.30.2