Received: by 2002:a05:6a10:eb17:0:0:0:0 with SMTP id hx23csp665867pxb; Thu, 9 Sep 2021 09:16:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeoH+F0AndotdvK0Mh1oI1NKE+QS1D7//LvwG2DW5uEr17s0LJ/XiUoyCv6th9KJuDxENE X-Received: by 2002:a17:906:b84a:: with SMTP id ga10mr4253868ejb.143.1631204209779; Thu, 09 Sep 2021 09:16:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631204209; cv=none; d=google.com; s=arc-20160816; b=gkEkr/PyCL0ugu9D3xBENOvl+jWhOHyPaoLI2UNi+y4iNjiphjvexNMx6VZsSQk0WC byI/rmOiV7EQ51iGniB1xUSQ92lbO5FuQuj35DzBm2z4pwDyBJ+XyxGUB6iO/zXVNEmH R22UIteTIA2ujmnjFCviYDDm1KEiUSJlmul3toLVR0pUylH1K8WL/IFfJ/I5pDM22vc+ jSgAh/LvK0FVsmW8ellSXiLi0IZTTnzCLfXoC/FMwZmEqrmn8WfUufEFkRyrIyEaTbaL 0qOyAXaVIj+IxWdGLhpALOJsg0ltI4zSOpnAEcoA7bpnNP3oHR/8xl28/e05xnKfRr5X MJKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=pACnzJlHMR2izPaEcZdZJlVxKc2mAvyrU+PyfYWuqjY=; b=WliYcVfGHumu6MTWYYSGyQPkwFPhYg3KWHZ3kvXtAbbhKIf7xQ/WcPmRHTcwqQMh9s WtlIcgfVUXRtlpB4ChfniMTAPutv0lWOLdjteFgI+Sdk/3dLeknmUS6krFw1DW/rpQ2X LqPPWsiV749x9cDbGRinpWZZTo/uly2PpU69xiFvRYIpH1p9gtEPWmD63rC6mEzbRHjp lAK7CwI4Q4ECJ+vw+YHH/vu6o4hyyq09LZSZ19v3NstaDIS3VRJ1flMefwqrWnIU8EF0 a2PZEBR9jsqxNlDbzXKglyxClubzJd/uYsMVvqXR25dmARYIJoj95L5hVr2yUyfMLJ3N ATqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t6b96zpr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y13si2795002edm.398.2021.09.09.09.16.18; Thu, 09 Sep 2021 09:16:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t6b96zpr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232894AbhIIQOl (ORCPT + 99 others); Thu, 9 Sep 2021 12:14:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232968AbhIIQOj (ORCPT ); Thu, 9 Sep 2021 12:14:39 -0400 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3D60C061575 for ; Thu, 9 Sep 2021 09:13:29 -0700 (PDT) Received: by mail-io1-xd2f.google.com with SMTP id g9so2986797ioq.11 for ; Thu, 09 Sep 2021 09:13:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pACnzJlHMR2izPaEcZdZJlVxKc2mAvyrU+PyfYWuqjY=; b=t6b96zprUu+yVzDHJupCAH73jnub/kQdWCLt5XJgNoL33Oiellv9B1ido23G4XTORY 7k9Hh37OLWFfZcZlwIJVrbE2YWyDirMOczoUQ6/EofSVVgQ+Ol8mrcRsTmFdzvzRv6wF elvTuv8Ea4SJP+CKYRit3qTfis4np14DXqIbiqW0B8J1mYwUI23q1FdzYQ+guyA4My+6 O00/IyGfcO6QP6VZc9+6jh//JSE2zz4WxNMOQPfZV8j0r9Zfgvxm5mHfBzyEKvoKGZdQ KD8m6joLHqL4VV3E3b0GgqeIETpWKbSItcDG/lvtFdw8lzZ9vAtF7VxS5rioJduy6ztD J3fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=pACnzJlHMR2izPaEcZdZJlVxKc2mAvyrU+PyfYWuqjY=; b=lYSYUVcbglE/iCwSWiD57QAhtone5cC+f1HpnMYFvd2Tz5XW4EWGmz4e6dlNsWxkob cdRTGQfwDHkzpwLTonS1f4eRmPG0oVXjWaYbVythuzQuM0xJcAxcMfTGuHSEoXqNXpg+ sOhTH1oNPz6pqLsj1/+2EyBcjEHK77rap/6/Ejx8ZsteFrGFK4Klm3ni4kmf2R4x8wqt 8WLIz/9qH4fWbbvfAslRMQ6B/HxHLk6m4PIwz/eIYTMSgewWEpW+M8Yztccn0UMgTrr2 vozUBr4cmHgkgfruz+hMeeTda6FO55q8asYqBzPyDovldRt/iiH3jBg8VuMZEQMhvOjJ rbgA== X-Gm-Message-State: AOAM5323e0rFV8qMsyj5sIYE4rWi5sxckQ9t/eUr/5x8RIgPYfK8E0bg +ZJmW4jSpQ+PWF1A/YERbPYrCrWDvrV6jz2SdgYtuw== X-Received: by 2002:a02:9204:: with SMTP id x4mr523733jag.45.1631204009109; Thu, 09 Sep 2021 09:13:29 -0700 (PDT) MIME-Version: 1.0 References: <8aa590be-6a9f-9343-e897-18e86ea48202@linaro.org> <6eefedb2-9e59-56d2-7703-2faf6cb0ca3a@codeaurora.org> <83ecbe74-caf0-6c42-e6f5-4887b3b534c6@linaro.org> <53d3e5b7-9dc0-a806-70e9-b9b5ff877462@codeaurora.org> In-Reply-To: From: Amit Pundir Date: Thu, 9 Sep 2021 21:42:52 +0530 Message-ID: Subject: Re: [PATCH] drm/msm: Disable frequency clamping on a630 To: Bjorn Andersson Cc: Akhil P Oommen , Caleb Connolly , Rob Clark , dri-devel , freedreno , linux-arm-msm , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Jonathan Marek , Sai Prakash Ranjan , open list , Stephen Boyd Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 9 Sept 2021 at 17:47, Amit Pundir wrote: > > On Wed, 8 Sept 2021 at 07:50, Bjorn Andersson > wrote: > > > > On Mon 09 Aug 10:26 PDT 2021, Akhil P Oommen wrote: > > > > > On 8/9/2021 9:48 PM, Caleb Connolly wrote: > > > > > > > > > > > > On 09/08/2021 17:12, Rob Clark wrote: > > > > > On Mon, Aug 9, 2021 at 7:52 AM Akhil P Oommen > > > > > wrote: > > [..] > > > > > > I am a bit confused. We don't define a power domain for gpu in dt, > > > > > > correct? Then what exactly set_opp do here? Do you think this usleep is > > > > > > what is helping here somehow to mask the issue? > > > > The power domains (for cx and gx) are defined in the GMU DT, the OPPs in > > > > the GPU DT. For the sake of simplicity I'll refer to the lowest > > > > frequency (257000000) and OPP level (RPMH_REGULATOR_LEVEL_LOW_SVS) as > > > > the "min" state, and the highest frequency (710000000) and OPP level > > > > (RPMH_REGULATOR_LEVEL_TURBO_L1) as the "max" state. These are defined in > > > > sdm845.dtsi under the gpu node. > > > > > > > > The new devfreq behaviour unmasks what I think is a driver bug, it > > > > inadvertently puts much more strain on the GPU regulators than they > > > > usually get. With the new behaviour the GPU jumps from it's min state to > > > > the max state and back again extremely rapidly under workloads as small > > > > as refreshing UI. Where previously the GPU would rarely if ever go above > > > > 342MHz when interacting with the device, it now jumps between min and > > > > max many times per second. > > > > > > > > If my understanding is correct, the current implementation of the GMU > > > > set freq is the following: > > > > - Get OPP for frequency to set > > > > - Push the frequency to the GMU - immediately updating the core clock > > > > - Call dev_pm_opp_set_opp() which triggers a notify chain, this winds > > > > up somewhere in power management code and causes the gx regulator level > > > > to be updated > > > > > > Nope. dev_pm_opp_set_opp() sets the bandwidth for gpu and nothing else. We > > > were using a different api earlier which got deprecated - > > > dev_pm_opp_set_bw(). > > > > > > > On the Lenovo Yoga C630 this is reproduced by starting alacritty and if > > I'm lucky I managed to hit a few keys before it crashes, so I spent a > > few hours looking into this as well... > > > > As you say, the dev_pm_opp_set_opp() will only cast a interconnect vote. > > The opp-level is just there for show and isn't used by anything, at > > least not on 845. > > > > Further more, I'm missing something in my tree, so the interconnect > > doesn't hit sync_state, and as such we're not actually scaling the > > buses. So the problem is not that Linux doesn't turn on the buses in > > time. > > > > So I suspect that the "AHB bus error" isn't saying that we turned off > > the bus, but rather that the GPU becomes unstable or something of that > > sort. > > > > > > Lastly, I reverted 9bc95570175a ("drm/msm: Devfreq tuning") and ran > > Aquarium for 20 minutes without a problem. I then switched the gpu > > devfreq governor to "userspace" and ran the following: > > > > while true; do > > echo 257000000 > /sys/class/devfreq/5000000.gpu/userspace/set_freq > > echo 710000000 > /sys/class/devfreq/5000000.gpu/userspace/set_freq > > done > > > > It took 19 iterations of this loop to crash the GPU. > > Ack. With your above script, I can reproduce a crash too on db845c > (A630) running v5.14. I didn't get any crash log though and device > just rebooted to USB crash mode. > > And same crash on RB5 (A650) too https://hastebin.com/raw/ejutetuwun fwiw I can't reproduce this crash on RB5 so far with v5.15-rc1 merge window (HEAD: 477f70cd2a67) > > > > > So the problem doesn't seem to be Rob's change, it's just that prior to > > it the chance to hitting it is way lower. Question is still what it is > > that we're triggering. > > > > Regards, > > Bjorn