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[23.128.96.18]) by mx.google.com with ESMTP id mp29si2639698ejc.290.2021.09.09.09.42.48; Thu, 09 Sep 2021 09:43:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20210112 header.b=m6C+xr8t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237735AbhIIQkU (ORCPT + 99 others); Thu, 9 Sep 2021 12:40:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237302AbhIIQkS (ORCPT ); Thu, 9 Sep 2021 12:40:18 -0400 Received: from mail-yb1-xb32.google.com (mail-yb1-xb32.google.com [IPv6:2607:f8b0:4864:20::b32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F37BC061575 for ; Thu, 9 Sep 2021 09:39:09 -0700 (PDT) Received: by mail-yb1-xb32.google.com with SMTP id v17so5087683ybs.9 for ; Thu, 09 Sep 2021 09:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=z6S9aCreq/0VGuneRW3q7amVuNejEfZAPRbvdWpbNPQ=; b=m6C+xr8tBL6hn8M8cZtiWUFtOEKpLOROHS4EvWaOJSbMPA7AjRIRr1vjbiUaLXdHri 9bChgFEoA7TNwaIB2TxgMA7wdFDJ9wlKq71tu4BLkfkS5MTzQ26PFHISd9tpV4M3imSE QGv01Iujhkw0xNImfBFO/zLPR8xyfFHJs5LYzOtGCVPAXXaOpZrLqwu9aW7BDbNX1jF9 bZyN/dJlHSEnfAZJhYmTl2j93j7oCs4u4IJoQL2RBGzQ3SrLvdei7URfW3nBY/I+KbnI 2fXNMFhGYk7bOI8C9+qndcbxbrCBqkwBQkMwJmF07nSgKWQvjwdtAF5XbVnq7umSh8Mf /Rvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=z6S9aCreq/0VGuneRW3q7amVuNejEfZAPRbvdWpbNPQ=; b=I4p4ec/uiCBa81vmio1mqrhObgbElMcwYMX4PBMky/QOrviBVk5VxPihNPzDXlJKv3 lROLh1B7OzyDTQc4W08sl/bEcE1XOYEUlMdDKPQCu7AyWk8/htVW/Vc4KXUUo4yNavCv 4V2rmWZj7HHWNWKiTnJDlIE74CmpyHAk4h44gAK6uoXJUYMNUlkE6jLA5Vms3GBqUx8E QDya54y8C8A28KBnerTRSsLe9gpxbM8zb76UrrTIn1bVohD85qkVLM4Vm+KNWoX6REz9 3ZnRKXFiZ1VRwj1yPbxIDKtxgAKj7fr54zB9KkDWJpmR2AHbF1t45yUFKXc1MtxVReIR fYmA== X-Gm-Message-State: AOAM531LNDR55YckMxsFSEKdOKnRsTAm+/QgpZd3RZ+ah5Mv4D2+VAmj YQ+Idr5hm8Kn/X70kQkAuHzrhMtNEXPE2SxVsgTUUQ== X-Received: by 2002:a25:21c5:: with SMTP id h188mr4685737ybh.23.1631205548028; Thu, 09 Sep 2021 09:39:08 -0700 (PDT) MIME-Version: 1.0 References: <20210909013818.1191270-1-rananta@google.com> <20210909013818.1191270-12-rananta@google.com> In-Reply-To: From: Raghavendra Rao Ananta Date: Thu, 9 Sep 2021 09:38:56 -0700 Message-ID: Subject: Re: [PATCH v4 11/18] KVM: arm64: selftests: Add basic GICv3 support To: Oliver Upton Cc: Paolo Bonzini , Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose , Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Reiji Watanabe , Jing Zhang , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 8, 2021 at 10:18 PM Oliver Upton wrote: > > On Thu, Sep 09, 2021 at 01:38:11AM +0000, Raghavendra Rao Ananta wrote: > > Add basic support for ARM Generic Interrupt Controller v3. > > The support provides guests to setup interrupts. > > > > The work is inspired from kvm-unit-tests and the kernel's > > GIC driver (drivers/irqchip/irq-gic-v3.c). > > > > Signed-off-by: Raghavendra Rao Ananta > > Reviewed-by: Andrew Jones > > --- > > tools/testing/selftests/kvm/Makefile | 2 +- > > .../selftests/kvm/include/aarch64/gic.h | 21 ++ > > tools/testing/selftests/kvm/lib/aarch64/gic.c | 93 +++++++ > > .../selftests/kvm/lib/aarch64/gic_private.h | 21 ++ > > .../selftests/kvm/lib/aarch64/gic_v3.c | 240 ++++++++++++++++++ > > .../selftests/kvm/lib/aarch64/gic_v3.h | 70 +++++ > > 6 files changed, 446 insertions(+), 1 deletion(-) > > create mode 100644 tools/testing/selftests/kvm/include/aarch64/gic.h > > create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic.c > > create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_private.h > > create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_v3.c > > create mode 100644 tools/testing/selftests/kvm/lib/aarch64/gic_v3.h > > > > [...] > > > +static void > > +gic_dist_init(enum gic_type type, unsigned int nr_cpus, void *dist_base) > > +{ > > + const struct gic_common_ops *gic_ops; > > does this need to be initialized? I haven't tried compiling, but it > seems it should trigger a compiler warning as it is only initialized if > type == GIC_V3. > Huh, I thought I had a default case covering this (must have gone lost during code reorg). Nice catch though! Surprisingly, the compiler never warned. I'm not sure if its smart enough to figure out that the caller of this function had GUEST_ASSERT(type < GIC_TYPE_MAX); Anyway, I'll clean it up. Regards, Raghavendra > > + spin_lock(&gic_lock); > > + > > + /* Distributor initialization is needed only once per VM */ > > + if (gic_common_ops) { > > + spin_unlock(&gic_lock); > > + return; > > + } > > + > > + if (type == GIC_V3) > > + gic_ops = &gicv3_ops; > > + > > + gic_ops->gic_init(nr_cpus, dist_base); > > + gic_common_ops = gic_ops; > > + > > + /* Make sure that the initialized data is visible to all the vCPUs */ > > + dsb(sy); > > + > > + spin_unlock(&gic_lock); > > +} >