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[23.128.96.18]) by mx.google.com with ESMTP id m8si2879765ejl.358.2021.09.09.11.32.23; Thu, 09 Sep 2021 11:32:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=gj+1nfSf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235943AbhIISam (ORCPT + 99 others); Thu, 9 Sep 2021 14:30:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229616AbhIISal (ORCPT ); Thu, 9 Sep 2021 14:30:41 -0400 Received: from mail-yb1-xb31.google.com (mail-yb1-xb31.google.com [IPv6:2607:f8b0:4864:20::b31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 577BEC061574 for ; Thu, 9 Sep 2021 11:29:31 -0700 (PDT) Received: by mail-yb1-xb31.google.com with SMTP id c6so5742732ybm.10 for ; Thu, 09 Sep 2021 11:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sfi0O5z3YUYhbW7zXo4IckbIgfrbajr/CKgbbY2Zyf4=; b=gj+1nfSfrs6Zv+O6sehty2rxFgfE2r+s0x7zwUZC+u+U0mXZzRWJkh+cB+Q5xjmkiO 3SRnImL9HDvlYj8Jfbm+DsrHk0TmO52i7ycoJnOA09deIWUfaE0JT1VtIggHWYd2/gFT W6xXUfTP0KotOdpRwzeW++EQyn67B0RUZ+RsA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sfi0O5z3YUYhbW7zXo4IckbIgfrbajr/CKgbbY2Zyf4=; b=YH2hqcG7VNZ1ZFyuWHi336ZZjIqMtq0R0WpWH9Z1dmZGVnzI12B/9KCAChFooUk5pJ 0HzoqrZeUCV5Lze7DAQ/1pwTcpQkajwBMBU35a008qkPxEOGLeyWkqyS7pHZpFKs/Ywj Nv05JmR48l2+1kLncuYib3/zG0HuBcwu0nGbLaW57aPb4qixbJ5sVAbR14d6Bpu7cnWU aJeSSlG2uOaD2OMvFZWci0L+mVuuYPpDULvltpu37JbNkKPlL7+lO1XMRTCPG6BrxZAE tGt22gnJbpPIyVok2LHCKQi3mtPDkbQJ07gpGK3jmnCB200yKDYl6Ph/NlsYWNCWi0Rw n6uQ== X-Gm-Message-State: AOAM533cyM8lhqfhgh1VG+jAXOszp8kV2D3UuV7MgF3LD4s1RA9QximG zD7rSo/j3+0MqXbFrskZOA6V3/zl4iDwwkhPRmGitQ== X-Received: by 2002:a25:478b:: with SMTP id u133mr5451813yba.532.1631212170654; Thu, 09 Sep 2021 11:29:30 -0700 (PDT) MIME-Version: 1.0 References: <20210908111500.1.I9f6dac462da830fa0a8ccccbe977ca918bf14e4a@changeid> In-Reply-To: From: Philip Chen Date: Thu, 9 Sep 2021 11:29:19 -0700 Message-ID: Subject: Re: [PATCH 1/2] drm/bridge: parade-ps8640: Use regmap APIs To: Stephen Boyd Cc: LKML , Douglas Anderson , Andrzej Hajda , Daniel Vetter , David Airlie , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Neil Armstrong , Robert Foss , dri-devel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, Sep 8, 2021 at 2:54 PM Stephen Boyd wrote: > > Quoting Philip Chen (2021-09-08 11:18:05) > > diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c > > index 685e9c38b2db..a16725dbf912 100644 > > --- a/drivers/gpu/drm/bridge/parade-ps8640.c > > +++ b/drivers/gpu/drm/bridge/parade-ps8640.c > > @@ -64,12 +65,29 @@ struct ps8640 { > > struct drm_bridge *panel_bridge; > > struct mipi_dsi_device *dsi; > > struct i2c_client *page[MAX_DEVS]; > > + struct regmap *regmap[MAX_DEVS]; > > struct regulator_bulk_data supplies[2]; > > struct gpio_desc *gpio_reset; > > struct gpio_desc *gpio_powerdown; > > bool powered; > > }; > > > > +static const struct regmap_range ps8640_volatile_ranges[] = { > > + { .range_min = 0, .range_max = 0xff }, > > Is the plan to fill this out later or is 0xff the max register? If it's > the latter then I think adding the max register to regmap_config is > simpler. It's the former. The real accessible register range is different per page, E.g.: - For page0, the register range is 0x00 - 0xbf. - For page1, the register range is 0x00 - 0xff. - For page2, the register range is 0x80 - 0xff. Even if we don't specify the accurate per-page register range later, the default register range here (0x00 - 0xff) can cover the available registers in each page. > > > +}; > > + > > +static const struct regmap_access_table ps8640_volatile_table = { > > + .yes_ranges = ps8640_volatile_ranges, > > + .n_yes_ranges = ARRAY_SIZE(ps8640_volatile_ranges), > > +}; > > + > > +static const struct regmap_config ps8640_regmap_config = { > > + .reg_bits = 8, > > + .val_bits = 8, > > + .volatile_table = &ps8640_volatile_table, > > + .cache_type = REGCACHE_NONE, > > +}; > > + > > static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) > > { > > return container_of(e, struct ps8640, bridge); > > @@ -78,13 +96,13 @@ static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) > > static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, > > const enum ps8640_vdo_control ctrl) > > { > > - struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; > > - u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; > > + struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; > > + u8 vdo_ctrl_buf[] = {VDO_CTL_ADD, ctrl}; > > Nitpick: Add a space after { and before }. Thanks. Will fix this in the next version. > > > int ret; > > > > - ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD, > > - sizeof(vdo_ctrl_buf), > > - vdo_ctrl_buf); > > + ret = regmap_bulk_write(map, PAGE3_SET_ADD, > > + vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); > > + > > if (ret < 0) { > > DRM_ERROR("failed to %sable VDO: %d\n", > > ctrl == ENABLE ? "en" : "dis", ret);