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[89.176.112.137]) by smtp.gmail.com with ESMTPSA id i9sm1956466wmi.44.2021.09.11.09.05.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 11 Sep 2021 09:05:37 -0700 (PDT) From: Marek Vasut Subject: Re: [PATCH AUTOSEL 5.14 12/32] PCI: rcar: Add L1 link state fix into data abort hook To: Sasha Levin , linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Marek Vasut , Lorenzo Pieralisi , Bjorn Helgaas , Geert Uytterhoeven , Wolfram Sang , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org, linux-pci@vger.kernel.org References: <20210911131149.284397-1-sashal@kernel.org> <20210911131149.284397-12-sashal@kernel.org> Message-ID: <6cbfadee-0d74-fa4c-9ef3-a1bce55632bb@gmail.com> Date: Sat, 11 Sep 2021 18:05:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210911131149.284397-12-sashal@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/11/21 3:11 PM, Sasha Levin wrote: > From: Marek Vasut > > [ Upstream commit a115b1bd3af0c2963e72f6e47143724c59251be6 ] > > When the link is in L1, hardware should return it to L0 > automatically whenever a transaction targets a component on the > other end of the link (PCIe r5.0, sec 5.2). > > The R-Car PCIe controller doesn't handle this transition correctly. > If the link is not in L0, an MMIO transaction targeting a downstream > device fails, and the controller reports an ARM imprecise external > abort. > > Work around this by hooking the abort handler so the driver can > detect this situation and help the hardware complete the link state > transition. > > When the R-Car controller receives a PM_ENTER_L1 DLLP from the > downstream component, it sets PMEL1RX bit in PMSR register, but then > the controller enters some sort of in-between state. A subsequent > MMIO transaction will fail, resulting in the external abort. The > abort handler detects this condition and completes the link state > transition by setting the L1IATN bit in PMCTLR and waiting for the > link state transition to complete. You will also need the following patch, otherwise the build will fail on configurations without COMMON_CLK (none where this driver is used, but happened on one of the build bots). I'm waiting for PCIe maintainers to pick it up: https://patchwork.kernel.org/project/linux-pci/patch/20210907144512.5238-1-marek.vasut@gmail.com/