Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Received-SPF: Pass (protection.outlook.com: domain of amd.com designates
 165.204.84.17 as permitted sender) receiver=protection.outlook.com;
 client-ip=165.204.84.17; helo=SATLEXMB04.amd.com;
Date:   Mon, 13 Sep 2021 16:11:34 +0800
From:   Huang Rui <ray.huang@amd.com>
To:     Peter Zijlstra <peterz@infradead.org>
CC:     "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Shuah Khan <skhan@linuxfoundation.org>,
        "Borislav Petkov" <bp@suse.de>, Ingo Molnar <mingo@kernel.org>,
        "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
        "Sharma, Deepak" <Deepak.Sharma@amd.com>,
        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "Limonciello, Mario" <Mario.Limonciello@amd.com>,
        "Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
        "Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
        "Du, Xiaojian" <Xiaojian.Du@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 04/19] cpufreq: amd: introduce a new amd pstate driver to
 support future processors
Message-ID: <20210913081134.GA3731830@hr-amd>
References: <20210908150001.3702552-1-ray.huang@amd.com>
 <20210908150001.3702552-5-ray.huang@amd.com>
 <YToh1Vhei2PyhlW+@hirez.programming.kicks-ass.net>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <YToh1Vhei2PyhlW+@hirez.programming.kicks-ass.net>
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2021 08:11:42.3224
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6fbeb0c3-ca8f-49a9-36db-08d9768e1ed4
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com]
X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1504
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Thu, Sep 09, 2021 at 11:01:41PM +0800, Peter Zijlstra wrote:
> On Wed, Sep 08, 2021 at 10:59:46PM +0800, Huang Rui wrote:
> 
> > +struct amd_pstate_perf_funcs {
> > +	int (*enable)(bool enable);
> > +	int (*init_perf)(struct amd_cpudata *cpudata);
> > +	void (*update_perf)(struct amd_cpudata *cpudata,
> > +			    u32 min_perf, u32 des_perf,
> > +			    u32 max_perf, bool fast_switch);
> > +};
> 
> > +static int
> > +amd_pstate_enable(struct amd_pstate_perf_funcs *funcs, bool enable)
> > +{
> > +	if (!funcs)
> > +		return -EINVAL;
> > +
> > +	return funcs->enable(enable);
> > +}
> 
> > +static int amd_pstate_init_perf(struct amd_cpudata *cpudata)
> > +{
> > +	struct amd_pstate_perf_funcs *funcs = cpufreq_get_driver_data();
> > +
> > +	if (!funcs)
> > +		return -EINVAL;
> > +
> > +	return funcs->init_perf(cpudata);
> > +}
> 
> > +static int
> > +amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
> > +		       u32 des_perf, u32 max_perf, bool fast_switch)
> > +{
> > +	struct amd_pstate_perf_funcs *funcs = cpufreq_get_driver_data();
> > +
> > +	if (!funcs)
> > +		return -EINVAL;
> > +
> > +	funcs->update_perf(cpudata, min_perf, des_perf,
> > +			   max_perf, fast_switch);
> > +
> > +	return 0;
> > +}
> 
> > +static struct amd_pstate_perf_funcs pstate_funcs = {
> > +	.enable = pstate_enable,
> > +	.init_perf = pstate_init_perf,
> > +	.update_perf = pstate_update_perf,
> > +};
> 
> > +static int __init amd_pstate_init(void)
> > +{
> > +	int ret;
> > +	struct amd_pstate_perf_funcs *funcs;
> 
> > +
> > +	funcs = &pstate_funcs;
> 
> What is the purpose of this seemingly pointless indirection? Showing off
> how good AMD hardware is at doing retpolines or something?

Hi Petter,

Thanks to look at our codes again. We adopt your suggestion which raised
about two year ago that using the kernel governors such as schedutil to
manage frequency control for new cpufreq driver.

We will have two approaches (it depends on different AMD processor
hardware) to implement the amd-pstate driver. (Please see details in Patch
19)

1) Full MSR Support
If current hardware has the full MSR support, we register "pstate_funcs"
callback functions to implement the MSR operations to control the clocks.

The reason that we use the separated way is that we can implement the
fast_switch or adjust_perf functions for schedutil and other governors. The
fast switch function can provide the better performance and lower latency
during frequency control.

2) Shared Memory Support
If current hardware doesn't have the full MSR support, that means it only
provides share memory support. We will leverage APIs in cppc_acpi libs with
"cppc_funcs" to implement the target function for the frequency control.


The mainly reasons that we proposed a new amd-pstate driver, not use the
existing acpi-freq or cppc-cpufreq driver are below:

1. As mentioned above, amd-pstate driver can implement
fast_switch/adjust_perf function with full MSR operations that have better
performance for schedutil and other governors.

2. We will implement the AMD specific features such as Energy Performance
Preference, Preferred Core, and etc. in the amd-pstate driver next step.

3. acpi-cpufreq and cppc-cpufreq are absolutely very good drivers which
provide the general solution for ACPI standards. However, 
- <i> if add amd-pstate similar support in acpi-cpufreq driver, it will
  impact the legacy P-States function on old Intel and AMD processors.
- <ii> if add amd-pstate similar the support in cppc-cpufreq driver, that
  will make this driver bring a lot of x86 specific or AMD specific changes
  (quirks or AMD specific handling) in the cppc-cpufreq driver, then the
  cppc-cpufreq driver won't be general anymore and will impact the existing
  ARM SOCs. And Rafael also didn't want me to add the x86/amd specific
  things in cppc-acpi before.

4. AMD will do the performance and power tunning or profiling on each AMD
CPU chip in future, different types of chips will have different policies.
For example, mobile chip and performance desktop problably have the
different frequency control policies.

5. We can maintain amd-pstate driver and handle the bugs which are reported
from community. Make sure it validated on each future and previous AMD CPU
processor, it can reduce the upstream maintenance work load. :-)

Best Regards,
Ray