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Wysocki" , Viresh Kumar , Shuah Khan , "Ingo Molnar" , "linux-pm@vger.kernel.org" , "Sharma, Deepak" , "Deucher, Alexander" , "Limonciello, Mario" , "Fontenot, Nathan" , "Su, Jinzhou (Joe)" , "Du, Xiaojian" , "linux-kernel@vger.kernel.org" , "x86@kernel.org" Subject: Re: [PATCH 01/19] x86/cpufreatures: add AMD CPPC extension feature flag Message-ID: <20210913094851.GB3731830@hr-amd> References: <20210908150001.3702552-1-ray.huang@amd.com> <20210908150001.3702552-2-ray.huang@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8af216e3-205c-4366-6cfc-08d9769bb5ce X-MS-TrafficTypeDiagnostic: DM5PR1201MB0252: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:597; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GD1gL0neXDTecTymXpIy7CSYd9i72xqb8TrZoZYsE1I9vkCwm0rzgV03M9BI04Rkdt7zZLlIoNCddSD5jDaxKe0FvNuNkNYPP3bGmPoeenVGTO4zePA9QijMeZnqiVGf2QIdCXVt5LK/3xTIWCtBFEGp5x4OqNfJhZnkBIcU/jjd1fv77441k94hDr0EmWCezYuGLi5rTwr6NMf3DzvKKuIQxadZ4sE5bHhg2JNAKM/7RPBttkpPiXYSau9uEAm3s9aLhGl9A//aFx0A+lN6/+Uw5GHkaM94nMer2KNxw4209hdtRHM2V+FNLr8PGJI3tEDYzHCoCeTlVvLwDoWf1LN+QhVFAZ324kUAWREpnDgsSY07Miu7gAMeM+ND3So7ERYHBzQRYNkJVRpQDz+A5KwHoYslzeaRmhXq5kIVoY71OL1N0a+2x4NHKfrM/Vu7MEOJdNqxcuUJ0yLhM3d6ckacvPt8waX+rYa8hTNuJI65WvbpamjtGJ6+IMF3aiBWDEvr+veGP+PLNDXEmWyV7GFZqUxEx+IKEYZ5Fw8nbDY2cw0eEOHSZiaB9o2UwYH5qOsHLqKgZet34BqclhPGS8bMsXdu6lYXfomSusq14mRPtu/PNlEuNi1crEMGRk1OgwbNdJzLPLbMYJQGA7vW7c6KgPrp155vcNT2fb7SaYfFwFQn1BPF2sK938akEQH+CmJ/vDE4OjW2uFIxv79XkNP2fELrEGRaMfLrmaybsRE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(136003)(376002)(346002)(39860400002)(396003)(36840700001)(46966006)(478600001)(70586007)(8936002)(82310400003)(5660300002)(356005)(6666004)(186003)(16526019)(47076005)(81166007)(9686003)(2906002)(4326008)(8676002)(70206006)(336012)(36860700001)(33656002)(33716001)(1076003)(55016002)(6916009)(26005)(316002)(82740400003)(54906003)(426003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2021 09:48:59.0849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8af216e3-205c-4366-6cfc-08d9769bb5ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0252 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Boris, On Fri, Sep 10, 2021 at 01:58:19AM +0800, Borislav Petkov wrote: > On Wed, Sep 08, 2021 at 10:59:43PM +0800, Huang Rui wrote: > > Add Collaborative Processor Performance Control Extension feature flag > > for AMD processors. > > > > Signed-off-by: Huang Rui > > --- > > arch/x86/include/asm/cpufeatures.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index d0ce5cfd3ac1..f7aea50e3371 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -313,6 +313,7 @@ > > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ > > +#define X86_FEATURE_AMD_CPPC_EXT (13*32+27) /* Collaborative Processor Performance Control Extension */ > > Why not simply X86_FEATURE_AMD_CPPC ? This feature flag indicates the full MSR hardware solution of AMD P-States, if it is not set, that means we will go with in shared memory hardware solution. So we name this as extension. I will explain the details in the commit log at V2. ;-) Thanks, Ray