Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp220985pxb; Mon, 13 Sep 2021 17:31:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVa1mjtXjrRPez74/sc2YBnioMRyhjy7k6AiqRoVHk1z1HOpWvHJIPseGzySfVv3JiCqOu X-Received: by 2002:a6b:3ec4:: with SMTP id l187mr11383323ioa.217.1631579486144; Mon, 13 Sep 2021 17:31:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631579486; cv=none; d=google.com; s=arc-20160816; b=PwekKgwIAXXOuYNsCsNt5GVKqBxzGro/PYP0L3yxL2kXehgV8XK4bBleuMKngaDL03 TdJ/+OzMr9KseDHr5DMhfEQBKWfYtu1sRMx09CtNNfdFTYouN0y2f+CR8a9jFmS5Mi+O iH3Wr9u9vGXOsbQx9rhkrxm4GcWvEQ9194E6/6wF/b/yKPA7P1bO/QDIAc46PFw7obxq +50ZPOSXkeh7DIQk+OOPtlOTFLtBM+a4Vpe+B9qK4ag/23zoHJ57MSicPIF4SwYvbW3U gp3vHX6Xt25ckgrLSS+35U165ydrBuklTaRcH3QcxXeaVv0s3vqNHP5zFeGdPtkdXdE3 hxMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KnVzsC5NaC7HpUUyNPzDRAHYEWP0W0Vea0KzNK5YnaI=; b=MzHOaoAFwluQV3Bpx1rEWZwWAjo2W5xrd8c8VS2nN9t4XTETgZN3k271eiZZg25xb5 mFLFnxLJkjwx6fosm0dGeYzmTBRtQv+SFqMhAp6ItyN2m7cUSaR+J4yzvHlkz7sLBwsR 668+ykbVHCIIElP6aXrvZEzPxatjPO3NHjpyTYWlYh8HLosy6QvQlIN6Klc+E6chZl1H AcyxXxgvHQSUWlhe36VSkJfY2r/zLzPRR+hDkwaxnGF5uZPgOWt92ieofUrjjWan4tF9 jmqMWmyTLY0BM3KLtvmycFhim/sriGq7iuOLrKaXemmXwqQErqnfOD2R4hq0wFe3gleD ctKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=a5F3pNRn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a3si8004006ioc.79.2021.09.13.17.31.15; Mon, 13 Sep 2021 17:31:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=a5F3pNRn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343935AbhIMOS0 (ORCPT + 99 others); Mon, 13 Sep 2021 10:18:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:60356 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344332AbhIMOLS (ORCPT ); Mon, 13 Sep 2021 10:11:18 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3E76961AAC; Mon, 13 Sep 2021 13:42:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1631540535; bh=TkOwg5YShF1JhjzsxjWb+eY/lSIENXcAsjTd/XtvOEQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a5F3pNRnB7Zb1GKBUoKMnTKPsbggMmTzEF5coyWh1o+N55X0a5TXKr33RQTcCYnM/ uqCvyQe1/QinFNj6o67PYLXaRoodMC+/zDEPT+dk0X+3FD4CdHyw5+YQYY+IsDT6le ofbgmozQrkg9XuVlwekLJg2iwfe4341nyAINR/BY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, =?UTF-8?q?Pali=20Roh=C3=A1r?= , Gregory CLEMENT , Sasha Levin Subject: [PATCH 5.13 201/300] arm64: dts: marvell: armada-37xx: Extend PCIe MEM space Date: Mon, 13 Sep 2021 15:14:22 +0200 Message-Id: <20210913131116.154750702@linuxfoundation.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210913131109.253835823@linuxfoundation.org> References: <20210913131109.253835823@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pali Rohár [ Upstream commit 514ef1e62d6521c2199d192b1c71b79d2aa21d5a ] Current PCIe MEM space of size 16 MB is not enough for some combination of PCIe cards (e.g. NVMe disk together with ath11k wifi card). ARM Trusted Firmware for Armada 3700 platform already assigns 128 MB for PCIe window, so extend PCIe MEM space to the end of 128 MB PCIe window which allows to allocate more PCIe BARs for more PCIe cards. Without this change some combination of PCIe cards cannot be used and kernel show error messages in dmesg during initialization: pci 0000:00:00.0: BAR 8: no space for [mem size 0x01800000] pci 0000:00:00.0: BAR 8: failed to assign [mem size 0x01800000] pci 0000:00:00.0: BAR 6: assigned [mem 0xe8000000-0xe80007ff pref] pci 0000:01:00.0: BAR 8: no space for [mem size 0x01800000] pci 0000:01:00.0: BAR 8: failed to assign [mem size 0x01800000] pci 0000:02:03.0: BAR 8: no space for [mem size 0x01000000] pci 0000:02:03.0: BAR 8: failed to assign [mem size 0x01000000] pci 0000:02:07.0: BAR 8: no space for [mem size 0x00100000] pci 0000:02:07.0: BAR 8: failed to assign [mem size 0x00100000] pci 0000:03:00.0: BAR 0: no space for [mem size 0x01000000 64bit] pci 0000:03:00.0: BAR 0: failed to assign [mem size 0x01000000 64bit] Due to bugs in U-Boot port for Turris Mox, the second range in Turris Mox kernel DTS file for PCIe must start at 16 MB offset. Otherwise U-Boot crashes during loading of kernel DTB file. This bug is present only in U-Boot code for Turris Mox and therefore other Armada 3700 devices are not affected by this bug. Bug is fixed in U-Boot version 2021.07. To not break booting new kernels on existing versions of U-Boot on Turris Mox, use first 16 MB range for IO and second range with rest of PCIe window for MEM. Signed-off-by: Pali Rohár Fixes: 76f6386b25cc ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700") Signed-off-by: Gregory CLEMENT Signed-off-by: Sasha Levin --- .../boot/dts/marvell/armada-3720-turris-mox.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index a05b1ab2dd12..04da07ae4420 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -135,6 +135,23 @@ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + /* + * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property + * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and + * 2 size cells and also expects that the second range starts at 16 MB offset. If these + * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address + * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window + * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. + * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in + * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): + * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 + * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf + * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 + */ + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ + 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ /* enabled by U-Boot if PCIe module is present */ status = "disabled"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 5db81a416cd6..9acc5d2b5a00 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -489,8 +489,15 @@ #interrupt-cells = <1>; msi-parent = <&pcie0>; msi-controller; - ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ - 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ + /* + * The 128 MiB address range [0xe8000000-0xf0000000] is + * dedicated for PCIe and can be assigned to 8 windows + * with size a power of two. Use one 64 KiB window for + * IO at the end and the remaining seven windows + * (totaling 127 MiB) for MEM. + */ + ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ + 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, -- 2.30.2