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[23.128.96.18]) by mx.google.com with ESMTP id z5si4594871edr.302.2021.09.13.20.59.23; Mon, 13 Sep 2021 20:59:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=Q+Stt1Ke; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239328AbhIND6r (ORCPT + 99 others); Mon, 13 Sep 2021 23:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239248AbhIND6l (ORCPT ); Mon, 13 Sep 2021 23:58:41 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33DD4C061574 for ; Mon, 13 Sep 2021 20:57:24 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id y6so21214420lje.2 for ; Mon, 13 Sep 2021 20:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Icmlo36/WeDJHtaQFlCSDhUmVMRzwC9n0IjehX7KX8s=; b=Q+Stt1KegkfalX84XgzXINRwOGd0RpR+6QUTPx0SZHBmm4C5qOIaMMChUxb/bvCa/q N+DnQnqm6E/I1cAep4msngrWAuY/dX3dTkfMWmKokV1THByzRpZo7loo3t9Et69P1DBW dYZRLPWhY699/X9g0RM5J+LuCSKCWqELM3ITE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Icmlo36/WeDJHtaQFlCSDhUmVMRzwC9n0IjehX7KX8s=; b=5eWii2pcpuGOxPLvRQPWhtMNsJdBVuVkCm/N7E/25qFpH5AZAv5DIIK6yznHUUmorH TKy+V2yjG03OQhdGu11p1AKKC3s/scbxSczVTJDlstNUWEICGGl6XbEhVqefe2N3Qm5A MIp8QmMx/phSZXr+kpcsRplARKNwjRzxVnV+qpSBUxCFHC1dcOtKKeA4Bx/NaVVJfgh5 iATMmbCa70DVXQFNRuANka5/Zuv4IkKRPq5TM4vw+yrmJ9U4hVfr1yB3oe66wSfCsr+D s0BhbPlxSnUjqoFsNGtqVQFYUVsDORPYkZQDKIIHQN5Ao8MzFkKQ719gl1X+0jpERG3J /pHQ== X-Gm-Message-State: AOAM533EYQLEKpa8rLE1amDauuefJAHomBCI6jfO0xiAn6gr5wJnJBCk ldULDGvlAnY/JMrFCUSnfx22Ks9/qbFjVhzojEpJjg== X-Received: by 2002:a2e:b52d:: with SMTP id z13mr13262840ljm.376.1631591842613; Mon, 13 Sep 2021 20:57:22 -0700 (PDT) MIME-Version: 1.0 References: <20210914021633.26377-1-chun-jie.chen@mediatek.com> <20210914021633.26377-10-chun-jie.chen@mediatek.com> In-Reply-To: <20210914021633.26377-10-chun-jie.chen@mediatek.com> From: Chen-Yu Tsai Date: Tue, 14 Sep 2021 11:57:11 +0800 Message-ID: Subject: Re: [v3 09/24] clk: mediatek: Add MT8195 infrastructure clock support To: Chun-Jie Chen Cc: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , LKML , "moderated list:ARM/Mediatek SoC support" , linux-clk , Devicetree List , srv_heupstream , Project_Global_Chrome_Upstream_Group Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 14, 2021 at 10:17 AM Chun-Jie Chen wrote: > > Add MT8195 infrastructure clock controller which provides > clock gate control for basic IP like pwm, uart, spi and so on. > > Signed-off-by: Chun-Jie Chen Reviewed-by: Chen-Yu Tsai