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[23.128.96.18]) by mx.google.com with ESMTP id i12si8226856jaf.41.2021.09.13.21.03.07; Mon, 13 Sep 2021 21:03:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=aymb2xNw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231282AbhINECZ (ORCPT + 99 others); Tue, 14 Sep 2021 00:02:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231245AbhINECY (ORCPT ); Tue, 14 Sep 2021 00:02:24 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89975C061574 for ; Mon, 13 Sep 2021 21:01:07 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id x27so25739570lfu.5 for ; Mon, 13 Sep 2021 21:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=iqV90RnceA3yUtnO20ku1+cBNKzKF42y3vDyfuFCg6I=; b=aymb2xNw9MWDQ5r1YExaL02R2WTT4y3lbBNUJ8uNopNlkPEkkjyy256PCafoeS7q7y UKpbxQcBXuQddeingdXPXg3aneXtL4WsuplQpEQZA1tHOcs+YufO5uCYTpjrRq27gWL5 BG0InFWVu3lKlC/PopTnD3xQ1A5NdkHpqMkC8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=iqV90RnceA3yUtnO20ku1+cBNKzKF42y3vDyfuFCg6I=; b=ar6s//6FIqsby258SRgYi22Pn8xfUx0MPFoha6BDnB+FQlnzBS1WlS1jLJRdjxpHbK 1S7ANtIMI/3YasHyuWSqjj/rvfwxtRsHRLd4sSsa3DGRDghLhmFphhpwmLt6VAE8cWF8 Qm6Ypr6oSct2Rvz8fjkochOcn6LEFRjWX+oYjaYgpVEF3b8XKpe6QpUT+BRdChmBSSu2 KujxgTT0NsK/QTN0cESqvTbjOWb2ADi//uUOQJRUasB/IhPDwBSs5t7GJ4P1IX+oq8gB OlkYNbX3HREL94qUWTWT1EGmCXtRfc4RqUxDkB3H2+dBQimNL7G4pO0VT9zRCgrr6i6i UmtQ== X-Gm-Message-State: AOAM532yr/juGmyG3QNjbJbVLOMFi5iYVGkhoFSu/G56FziDgz9Ddev/ 4l4xEVvu46vwdf/+0EdAu2Z278gQxGcoNRSEAy3smHmfjOthUA== X-Received: by 2002:ac2:5d71:: with SMTP id h17mr11277423lft.670.1631592065978; Mon, 13 Sep 2021 21:01:05 -0700 (PDT) MIME-Version: 1.0 References: <20210914021633.26377-1-chun-jie.chen@mediatek.com> <20210914021633.26377-19-chun-jie.chen@mediatek.com> In-Reply-To: <20210914021633.26377-19-chun-jie.chen@mediatek.com> From: Chen-Yu Tsai Date: Tue, 14 Sep 2021 12:00:55 +0800 Message-ID: Subject: Re: [v3 18/24] clk: mediatek: Add MT8195 vdosys1 clock support To: Chun-Jie Chen Cc: Matthias Brugger , Stephen Boyd , Nicolas Boichat , Rob Herring , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , LKML , "moderated list:ARM/Mediatek SoC support" , linux-clk , Devicetree List , srv_heupstream , Project_Global_Chrome_Upstream_Group Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 14, 2021 at 10:18 AM Chun-Jie Chen wrote: > > Add MT8195 vdosys1 clock controller which provides clock gate > control in video system. This is integrated with mtk-mmsys > driver which will populate device by platform_device_register_data > to start vdosys clock driver. > > Signed-off-by: Chun-Jie Chen Reviewed-by: Chen-Yu Tsai