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[23.128.96.18]) by mx.google.com with ESMTP id e4si1040382ili.160.2021.09.14.02.37.46; Tue, 14 Sep 2021 02:37:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=iZtLCyi9; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=D9cIWhv9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231479AbhINJgy (ORCPT + 99 others); Tue, 14 Sep 2021 05:36:54 -0400 Received: from wnew4-smtp.messagingengine.com ([64.147.123.18]:53623 "EHLO wnew4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbhINJgq (ORCPT ); Tue, 14 Sep 2021 05:36:46 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailnew.west.internal (Postfix) with ESMTP id A0D132B012D1; Tue, 14 Sep 2021 05:35:27 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Tue, 14 Sep 2021 05:35:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=vGRGc5msdaUUt N2Q/hEpOdZOoPgZX0N6pFbxp/JPVss=; b=iZtLCyi9wFRsqeqp+Pn88WCe/klKA o9zn8SMryAZKaVbWAawd6nfJ8OiE4rbAuNHOQYTzDPKFb29UvmQm20WEvGxLjSJl qeYW0XR7md+Z0sDdTyjG5aaLnql/uFzBkKd58Kpro0DXlEV3gchFh6ewYQb4sxhe r4Zqu93DN+lOzsT9C7iEnPzT1iS3EOTOSv2x6jVR6U/LkAD1fya6f1o140ilzO3/ bjELQ7z+i4Qe45XCNDiLcvTl2y0EukH5X4MY0JcAeuYXyXTDLO/6rqC3o5tZoF2/ fEdsZn0fph22OQM/q1GvHbVpEZJAbJTooEivrG2acTPkmeSWQSHnHzcaw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=vGRGc5msdaUUtN2Q/hEpOdZOoPgZX0N6pFbxp/JPVss=; b=D9cIWhv9 V/yAl0NZquUorK4TPBJap/U9U8HYE5M6YkoUAd1w1o0WqhsypH1lGkMwitpG6SBh lW2f/LdI8r6BxA0WrSaNh7qUiQwo9EByIjLrGh9N1Wl9/SZVsj917kLNWlA1gyn3 ojvJaXhTjsrQPDH0Ry/CS8EjJA6+RXQ5i8+/7+5AEO7lCCggOzrJWQ8VGpzew3t9 Fs+j1gGYtCIxUma0yoXdyGlzq5dmADZ5q/j1CE/NwkCcXHVqM7ma2vRIjJHngKW6 f1TiCb1pke+jYnF2S1V207pR1qby7jzZPT9tuilzY6K/FeQjXb8ZoFI56zAIO/Ww vQlirGeWNgKazw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudegledgudeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepvdekleevfeffkeejhfffueelteelfeduieefheduudfggffhhfffheevveeh hedvnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmh grgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 14 Sep 2021 05:35:26 -0400 (EDT) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , dri-devel@lists.freedesktop.org, Daniel Vetter , David Airlie , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard Cc: Maxime Ripard , linux-clk@vger.kernel.org, Dave Stevenson , Phil Elwell , Tim Gover , Dom Cobley , Emma Anholt , linux-kernel@vger.kernel.org, Russell King Subject: [PATCH v2 2/3] drm/vc4: hdmi: Convert to the new clock request API Date: Tue, 14 Sep 2021 11:35:14 +0200 Message-Id: <20210914093515.260031-3-maxime@cerno.tech> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210914093515.260031-1-maxime@cerno.tech> References: <20210914093515.260031-1-maxime@cerno.tech> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The new clock request API allows us to increase the rate of the HSM clock to match our pixel rate requirements while decreasing it when we're done, resulting in a better power-efficiency. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++++----- drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 4a1115043114..099a94570e86 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -635,6 +635,8 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, vc4_hdmi->variant->phy_disable(vc4_hdmi); clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); + clk_request_done(vc4_hdmi->bvb_req); + clk_request_done(vc4_hdmi->hsm_req); clk_disable_unprepare(vc4_hdmi->pixel_clock); ret = pm_runtime_put(&vc4_hdmi->pdev->dev); @@ -941,9 +943,9 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, * pixel clock, but HSM ends up being the limiting factor. */ hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); - ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); - if (ret) { - DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); + vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate); + if (IS_ERR(vc4_hdmi->hsm_req)) { + DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req)); return; } @@ -956,9 +958,10 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, else bvb_rate = 75000000; - ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); + vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate); if (ret) { - DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); + DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req)); + clk_request_done(vc4_hdmi->hsm_req); clk_disable_unprepare(vc4_hdmi->pixel_clock); return; } @@ -966,6 +969,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); if (ret) { DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); + clk_request_done(vc4_hdmi->bvb_req); + clk_request_done(vc4_hdmi->hsm_req); clk_disable_unprepare(vc4_hdmi->pixel_clock); return; } diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h index 33e9f665ab8e..683b2d8a3dca 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h @@ -176,6 +176,9 @@ struct vc4_hdmi { struct reset_control *reset; + struct clk_request *bvb_req; + struct clk_request *hsm_req; + struct debugfs_regset32 hdmi_regset; struct debugfs_regset32 hd_regset; }; -- 2.31.1