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Date:   Tue, 14 Sep 2021 18:29:55 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Gerhard Engleder <gerhard@engleder-embedded.com>
Cc:     Vladimir Oltean <vladimir.oltean@nxp.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        netdev <netdev@vger.kernel.org>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Russell King <linux@armlinux.org.uk>,
        Jakub Kicinski <kuba@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH net] Revert "net: phy: Uniform PHY driver access"
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> I submitted it, but Michal Simek argumented that dts files of FPGA
> logic shall not be part of mainline. I suggested that at least one
> reference platform for every FPGA based IP core should be allowed,
> but he said that no one is able to test it.  So it seems that you
> will never see any dts file which contains FPGA logic in mainline. I
> will try to submit it again if anyone will support me?

My opinion: If there is a real product out in the field using this,
the DT for the product can be in mainline.

Reference Design Kits for ASICs are well supported in mainline. So the
question is, is an FPGA sufficiently different to an ASIC that is
should be treated differently? Do you have an off the shelf platform
or something custom? How easy is it to get the platform which is used
as an RDK? Can you make a bitstream available for anybody to use?

	Andrew