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[23.128.96.18]) by mx.google.com with ESMTP id g2si12223849iob.28.2021.09.14.15.36.08; Tue, 14 Sep 2021 15:36:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20210112 header.b=CjFqjry3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235642AbhINWg0 (ORCPT + 99 others); Tue, 14 Sep 2021 18:36:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236072AbhINWdV (ORCPT ); Tue, 14 Sep 2021 18:33:21 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9211FC061764 for ; Tue, 14 Sep 2021 15:31:47 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id p200-20020a25d8d1000000b005a3a281bc11so1038022ybg.0 for ; Tue, 14 Sep 2021 15:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=ap1ftYDLPyFEEpyKZVnsUXcIKPkxVpyeCr5WbufecSE=; b=CjFqjry3wo3EQPMz5M99dDU9C/SJybGkzsqWG/YDHqzkvfrMClsP6/tYCnkQ6mabGN ciRWxPdsotKE2bFCar/MqFTkNSNrjzafeoEsbrVqtUP1YHsQ5oA7EzkCrWaS3DUV8edz /wQ2KKAXSnINeEpXioFtHmJs2fA6eGzFjENcKZjm8/kYZUTvinu8Zf5CYFKRn1bW+iwW /yuPsTBbs6j43kZgKAReV/AbVhWd/mZC09YjNPzfAi5zRCsUYVQmqdi7wyvLj5Hm+sEO 1+iFZ9J9NQurs9j2BCPUcxJdDOC/ao0/6qc1mJBn4hWI5TvP5xxL2glsMvmkZuY8U+uJ fKYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=ap1ftYDLPyFEEpyKZVnsUXcIKPkxVpyeCr5WbufecSE=; b=VVtLrmbTe2xT5ICnpQVadRAKqKhLuIaiQgHBjDKxosWd0xXDidlNaE2jwc3plE5nAf FNcY/46sujUbbMsADFeppNGx+B4gxcW+yY+iLdJxnX/rhgwPaHxJ5JV/D/7UsA/MSauy GEFQhnf883RiXt4LCRYK2iLdZtn4sT4GF5buCKbrSjS2NYyy2Gow9C9M8kTax4rYs+FT +Imde91sWrsFzIZZ6+oWR6ibxjWitNZ2xEwIq0BlFpQVCwS2815HRjZeM/9qvQJcSc6e /FjxwgZsQyJJl6N9By4hl4FY7R9OCuAM5lwD/it9WcjVicDSeulGYmJWMOUy0MJ0PKB8 XbCA== X-Gm-Message-State: AOAM531Z9NXVo9wLhO+2DBGVP0zpwZNeo8PhM0vBfK3FC6YMuwm7wXGR elXCbT3yEvZ7EgXhVFu/6d8hJwYIRWSI X-Received: from rananta-virt.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1bcc]) (user=rananta job=sendgmr) by 2002:a25:16c6:: with SMTP id 189mr1901322ybw.27.1631658706802; Tue, 14 Sep 2021 15:31:46 -0700 (PDT) Date: Tue, 14 Sep 2021 22:31:10 +0000 In-Reply-To: <20210914223114.435273-1-rananta@google.com> Message-Id: <20210914223114.435273-12-rananta@google.com> Mime-Version: 1.0 References: <20210914223114.435273-1-rananta@google.com> X-Mailer: git-send-email 2.33.0.309.g3052b89438-goog Subject: [PATCH v7 11/15] KVM: arm64: selftests: Add light-weight spinlock support From: Raghavendra Rao Ananta To: Paolo Bonzini , Marc Zyngier , Andrew Jones , James Morse , Alexandru Elisei , Suzuki K Poulose Cc: Catalin Marinas , Will Deacon , Peter Shier , Ricardo Koller , Oliver Upton , Reiji Watanabe , Jing Zhang , Raghavendra Rao Anata , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a simpler version of spinlock support for ARM64 for the guests to use. The implementation is loosely based on the spinlock implementation in kvm-unit-tests. Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Oliver Upton Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/Makefile | 2 +- .../selftests/kvm/include/aarch64/spinlock.h | 13 +++++++++ .../selftests/kvm/lib/aarch64/spinlock.c | 27 +++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/kvm/include/aarch64/spinlock.h create mode 100644 tools/testing/selftests/kvm/lib/aarch64/spinlock.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 5d05801ab816..61f0d376af99 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -35,7 +35,7 @@ endif LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S -LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S +LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test diff --git a/tools/testing/selftests/kvm/include/aarch64/spinlock.h b/tools/testing/selftests/kvm/include/aarch64/spinlock.h new file mode 100644 index 000000000000..cf0984106d14 --- /dev/null +++ b/tools/testing/selftests/kvm/include/aarch64/spinlock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef SELFTEST_KVM_ARM64_SPINLOCK_H +#define SELFTEST_KVM_ARM64_SPINLOCK_H + +struct spinlock { + int v; +}; + +extern void spin_lock(struct spinlock *lock); +extern void spin_unlock(struct spinlock *lock); + +#endif /* SELFTEST_KVM_ARM64_SPINLOCK_H */ diff --git a/tools/testing/selftests/kvm/lib/aarch64/spinlock.c b/tools/testing/selftests/kvm/lib/aarch64/spinlock.c new file mode 100644 index 000000000000..a076e780be5d --- /dev/null +++ b/tools/testing/selftests/kvm/lib/aarch64/spinlock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ARM64 Spinlock support + */ +#include + +#include "spinlock.h" + +void spin_lock(struct spinlock *lock) +{ + int val, res; + + asm volatile( + "1: ldaxr %w0, [%2]\n" + " cbnz %w0, 1b\n" + " mov %w0, #1\n" + " stxr %w1, %w0, [%2]\n" + " cbnz %w1, 1b\n" + : "=&r" (val), "=&r" (res) + : "r" (&lock->v) + : "memory"); +} + +void spin_unlock(struct spinlock *lock) +{ + asm volatile("stlr wzr, [%0]\n" : : "r" (&lock->v) : "memory"); +} -- 2.33.0.309.g3052b89438-goog