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[84.20.244.219]) by smtp.gmail.com with ESMTPSA id b14sm1221085edy.56.2021.09.16.03.26.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Sep 2021 03:26:07 -0700 (PDT) Subject: Re: [PATCH v2 1/2] power: supply: max17042_battery: Clear status bits in interrupt handler To: Sebastian Krzyszkowiak , Sebastian Reichel , linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Dirk Brandewie , kernel@puri.sm, stable@vger.kernel.org References: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> From: Krzysztof Kozlowski Message-ID: <42c74aa4-55ef-194b-b26c-945399d16a4b@canonical.com> Date: Thu, 16 Sep 2021 12:26:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210914121806.1301131-1-sebastian.krzyszkowiak@puri.sm> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/09/2021 14:18, Sebastian Krzyszkowiak wrote: > The gauge requires us to clear the status bits manually for some alerts > to be properly dismissed. Previously the IRQ was configured to react only > on falling edge, which wasn't technically correct (the ALRT line is active > low), but it had a happy side-effect of preventing interrupt storms > on uncleared alerts from happening. > > Fixes: 7fbf6b731bca ("power: supply: max17042: Do not enforce (incorrect) interrupt trigger type") > Cc: > Signed-off-by: Sebastian Krzyszkowiak > --- > v2: added a comment on why it clears all alert bits > --- > drivers/power/supply/max17042_battery.c | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof