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From:   Chen Huang <chenhuang5@huawei.com>
To:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
CC:     Chen Huang <chenhuang5@huawei.com>,
        Kefeng Wang <wangkefeng.wang@huawei.com>,
        Darius Rad <darius@bluespec.com>,
        Jisheng Zhang <jszhang3@mail.ustc.edu.cn>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 0/2] riscv: improve unaligned memory accesses
Date:   Thu, 16 Sep 2021 13:08:53 +0000
Message-ID: <20210916130855.4054926-1-chenhuang5@huawei.com>
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The patchset improves RISCV unaligned memory accesses, selects
HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
of unaligned memory accesses.

If CPU don't support unaligned memory accesses for now, please
select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
don't support unaligned memory accesses, I don't choose the
CONFIG for them.

Changes since v1:
 - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
   unaligned memory accesses, add an option for CPUs to choose it or not.

Chen Huang (2):
  riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
  riscv: Support DCACHE_WORD_ACCESS

 arch/riscv/Kconfig                      |  5 ++++
 arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

-- 
2.25.1