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Date:   Thu, 16 Sep 2021 16:05:47 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Asmaa Mnebhi <asmaa@nvidia.com>
Cc:     andy.shevchenko@gmail.com, linux-gpio@vger.kernel.org,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-acpi@vger.kernel.org, kuba@kernel.org,
        linus.walleij@linaro.org, bgolaszewski@baylibre.com,
        davem@davemloft.net, rjw@rjwysocki.net, davthompson@nvidia.com
Subject: Re: [PATCH v1 1/2] gpio: mlxbf2: Introduce IRQ support
Message-ID: <YUNPO9/YacBNr/yQ@lunn.ch>
References: <20210915222847.10239-1-asmaa@nvidia.com>
 <20210915222847.10239-2-asmaa@nvidia.com>
MIME-Version: 1.0
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In-Reply-To: <20210915222847.10239-2-asmaa@nvidia.com>
Precedence: bulk

> +static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
> +{
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
> +	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
> +	int offset = irqd_to_hwirq(irqd);
> +	unsigned long flags;
> +	u32 val;
> +
> +	spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
> +	val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
> +	val |= BIT(offset);
> +	writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
> +
> +	/* Enable PHY interrupt by setting the priority level */

This should be an abstract driver for a collection of GPIO lines.
Yes, one of these GPIOs is used for the PHY, but the GPIO driver does
not care. So please remove this comment.

> +	val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
> +	val |= BIT(offset);
> +	writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);

What exactly does this do? It appears to clear the interrupt, if i
understand mlxbf2_gpio_irq_handler(). I don't know the GPIO framework
well enough to know if this is correct. It does mean if the interrupt
signal is active but masked, and you enable it, you appear to loose
the interrupt? Maybe you want the interrupt to fire as soon as it is
enabled?

> +static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
> +{
> +	struct mlxbf2_gpio_context *gs = ptr;
> +	struct gpio_chip *gc = &gs->gc;
> +	unsigned long pending;
> +	u32 level;
> +
> +	pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
> +	writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
> +
> +	for_each_set_bit(level, &pending, gc->ngpio) {
> +		int gpio_irq = irq_find_mapping(gc->irq.domain, level);
> +		generic_handle_irq(gpio_irq);
> +	}
> +
> +	return IRQ_RETVAL(pending);
> +}
> +
> +static void mlxbf2_gpio_irq_mask(struct irq_data *irqd) {
> +	mlxbf2_gpio_irq_disable(irqd);
> +}
> +
> +static void mlxbf2_gpio_irq_unmask(struct irq_data *irqd) {
> +	mlxbf2_gpio_irq_enable(irqd);
> +}

Do these two functions have any value?

> +static int
> +mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
> +{
> +	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
> +	struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
> +	int offset = irqd_to_hwirq(irqd);
> +	unsigned long flags;
> +	bool fall = false;
> +	bool rise = false;
> +	u32 val;
> +
> +	switch (type & IRQ_TYPE_SENSE_MASK) {
> +	case IRQ_TYPE_EDGE_BOTH:
> +	case IRQ_TYPE_LEVEL_MASK:
> +		fall = true;
> +		rise = true;
> +		break;
> +	case IRQ_TYPE_EDGE_RISING:
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		rise = true;
> +		break;
> +	case IRQ_TYPE_EDGE_FALLING:
> +	case IRQ_TYPE_LEVEL_LOW:
> +		fall = true;
> +		break;

This looks wrong. You cannot map a level interrupt into an edge. It
looks like your hardware only supports edges. If asked to do level,
return -EINVAL.

> +	default:
> +		break;
> +	}
> +
> +	/* The INT_N interrupt level is active low.
> +	 * So enable cause fall bit to detect when GPIO
> +	 * state goes low.
> +	 */

I don't understand this comment.

  Andrew