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Date:   Thu, 16 Sep 2021 15:13:23 -0500
From:   Rob Herring <robh@kernel.org>
To:     Bhaskara Budiredla <bbudiredla@marvell.com>
Cc:     robh+dt@kernel.org, sgoutham@marvell.com,
        linux-kernel@vger.kernel.org, will@kernel.org,
        linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com,
        devicetree@vger.kernel.org
Subject: Re: [PATCH v5 2/2] dt-bindings: perf: Add YAML schemas for Marvell
 CN10K LLC-TAD pmu bindings
Message-ID: <YUOlY68fgN9TcNr1@robh.at.kernel.org>
References: <20210908120425.10084-1-bbudiredla@marvell.com>
 <20210908120425.10084-3-bbudiredla@marvell.com>
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On Wed, 08 Sep 2021 17:34:25 +0530, Bhaskara Budiredla wrote:
> Add device tree bindings for Last-level-cache Tag-and-data
> (LLC-TAD) unit PMU for Marvell CN10K SoCs.
> 
> Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com>
> ---
>  .../bindings/perf/marvell-cn10k-tad.yaml      | 63 +++++++++++++++++++
>  1 file changed, 63 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>